原创 DC compile_ultra命令

2.  Synopsys Commands                                        Command Reference
                                 compile_ultra

NAME
       compile_ultra
              Performs  a high-effort compile on the current design for better
              quality of results (QoR).

SYNTAX
       status compile_ultra
              [-incremental]
              [-scan]
              [-exact_map]
              [-no_autoungroup]
              [-no_seq_output_inversion]
              [-no_boundary_optimization]
              [-no_design_rule | -only_design_rule]
              [-timing_high_effort_script | -area_high_effort_script]
              [-top]
              [-retime]
              [-gate_clock]
              [-check_only]
              [-num_cpus n]
              [-congestion]

   Data Types
       n     integer

ARGUMENTS
       -incremental
              Runs compile_ultra in incremental mode.  In the incremental mode
              the  tool  does  not  run  mapping  or  implementation selection
              stages.

       -scan  Enables the examination of the impact of scan insertion on  mis-
              sion  mode  constraints during optimization, as in a normal com-
              pile.  Use this option to replace all sequential elements during
              optimization.   Some  scan-replaced sequential cells may be con-
              verted to nonscan cells later  in  the  test  synthesis  process
              because of test design rule violations or explicit user specifi-
              cations.

       -exact_map
              Specifies that sequential cells are mapped exactly as  indicated
              in HDL.

       -no_autoungroup
              Specifies that automatic ungrouping is completely disabled.  All
              user hierarchies are preserved unless otherwise specified.

       -no_seq_output_inversion
              Disables sequential output inversion.  The phase  sequential  of
              all  sequential  elements  will be the same as the RTL.  Without
              this option, compile_ultra is free to invert sequential elements
              during  mapping and optimization.  For more information, see the
              man page for  the  compile_seqmap_enable_output_inversion  vari-
              able.

       -no_boundary_optimization
              Specifies  that  no  hierarchical boundary optimization is to be
              performed.  By default, boundary optimization is turned on  dur-
              ing compile_ultra activity.

       -no_design_rule
              Determines  whether  the  command  fixes  design rule violations
              before exiting.  The -no_design_rule option  specifies  for  the
              command  to  exit  before  fixing  design  rule violations, thus
              allowing you to check the results in a constraint report  before
              fixing  the  violations.   The default is to perform both design
              rule fixing and mapping optimizations before exiting.

              The -no_design_rule and -only_design_rule options  are  mutually
              exclusive.  Use only one option.

       -only_design_rule
              Determines  whether  the  command  fixes  design rule violations
              before exiting.  The -only_design_rule option specifies for  the
              command  to  perform  only  design rule fixing; that is, mapping
              optimizations are not performed.  The default is to perform both
              design rule fixing and mapping optimizations before exiting.

              The  -no_design_rule  and -only_design_rule options are mutually
              exclusive.  Use only one option.  The  -only_design_rule  option
              can be used only with the -incremental option.

       -timing_high_effort_script
              Runs  a  strategy intended to improve the resulting delay of the
              design, possibly at the cost of additional runtime.  The  strat-
              egy  may  make  changes  to variables or constraints that modify
              compile_ultra behavior and perform additional passes to  achieve
              better delay.

       -area_high_effort_script
              Runs  a  strategy  intended to improve the resulting area of the
              design, possibly at the cost of additional runtime.  The  strat-
              egy  may  make  changes  to variables or constraints that modify
              compile_ultra behavior and perform additional passes to  achieve
              better area.

       -top   Fixes  design  rule and top-level timing violations in a design.
              By default, this option fixes all design  rule  violations,  but
              only those timing violations whose paths cross top-level hierar-
              chical boundaries.  If you want this option to fix timing viola-
              tions  for  all paths, set the compile_top_all_paths variable to
              true.

       -retime
              Uses the adaptive  retiming  algorithm  during  optimization  to
              improve delay.  This option is ignored if the -only_design_rule,
              -incremental, or -top options are chosen at the same time.

       -gate_clock
              Enables clock gating optimization: clock gates are automatically
              inserted  or removed.  If the power_driven_clock_gating variable
              is set to true, the  optimization  is  based  on  the  switching
              activity   and   dynamic  power  of  the  register  banks.   The
              -gate_clock option  cannot  be  used  in  combination  with  the
              -only_design_rule option.  When used with the -exact_map option,
              it may not be possible to honor the -exact_map option for  those
              registers that are involved with clock gating optimization.

       -check_only
              Checks  whether  the  design  and libraries have all of the data
              that compile_ultra requires to run successfully.  This option is
              available only in Design Compiler topographical mode.

       -num_cpus n
              Specifies  the  number of CPUs to use during compile.  The value
              can range from 0 to 16.  The default value is 0.

       -congestion
              Enables Design Compiler features to optimize for  reduced  rout-
              ing-related congestion.  This option is only supported in Design
              Compiler topographical mode.

DESCRIPTION
       The compile_ultra command performs a high-effort compile on the current
       design  for better quality of results (QoR).  Like the compile command,
       optimization is controlled by  constraints  that  you  specify  on  the
       design.  This command is targeted towards high performance designs with
       very tight timing constraints.  It provides you with a simple push-but-
       ton approach to achieve critical delay optimization.  The compile_ultra
       command packages all of the Design Compiler  Ultra  features  and  have
       them  on by default.  It requires a Design Compiler Ultra license, plus
       a DesignWare Foundation license.  This command provides the best strat-
       egy for optimum overall QoR and performance.

       This command can be used in the same manner as the compile command.

       By  default,  compile_ultra incorporates two ungrouping phases for user
       design hierarchies.  The first phase is performed  before  "Pass1  Map-
       ping"  and  attempts  to  ungroup small design hierarchies.  This first
       ungrouping phase can be turned off using the following command:

         set compile_ultra_ungroup_small_hierarchies false

       The second ungrouping phase is performed during "Mapping  Optimization"
       and  applies  a delay-based ungrouping strategy for user design hierar-
       chies.  You can set variables to control the second ungrouping phase in
       the  same manner as with compile -auto_ungroup delay; for example, with
       the compile_auto_ungroup_delay_num_cells variable.  If you need to pre-
       serve all user design hierarchies, use the -no_autoungroup option.

       By default, if dw_foundation.sldb is not in the synthetic_library list,
       and the DesignWare license  is  successfully  checked  out,  dw_founda-
       tion.sldb  is  automatically  added to the synthetic_library to utilize
       the QoR benefit provided  by  the  licensed  DesignWare  architectures.
       This  behavior  occurs  in  the  current  command only, and it does not
       affect the user-specified synthetic_library and link_library list.

       By default, all DesignWare hierarchies are unconditionally ungrouped in
       the  second  pass of compile.  You can set the compile_ultra_ungroup_dw
       variable to control the ungrouping process of DesignWare components.

       By default, hierarchical boundary  optimization  is  performed  on  the
       design.   This  can  change  the  function of the design so that it can
       operate only in its current environment.  If input or output ports  are
       complemented  as  a result of this optimization, port names are changed
       according  to  the  port_complement_naming_style  variable.   Use   the
       -no_boundary_optimization  option to turn off the boundary optimization
       feature.

       Regardless of the options used, compile_ultra sets the  value  for  the
       following environment variables:

         hlo_resource_allocation = constraint_driven
         hlo_resource_implementation = use_fastest
         hlo_minimize_tree_delay = true
         compile_use_low_timing_effort = false
         compile_implementation_selection = true

       The -area_high_effort_script and -timing_high_effort_script options run
       prepared scripts intended to improve the area or delay of  the  design.
       The  scripts apply a compile strategy that may turn on or off different
       optimization features depending on the optimization goal, and may  make
       temporary  changes to optimization constraints.  Therefore, using these
       scripts may override additional variables not mentioned in the previous
       paragraph.   Some variable settings may persist after the compile_ultra
       command completes, so that subsequent incremental compiles run with the
       same  settings.   Because  the  scripts  may perform additional compile
       passes, they may increase the runtime  of  the  compile_ultra  command.
       These   two   options   cannot   be   used   with   the   -incremental,
       -no_design_rule, or -only_design_rule option.

EXAMPLES
       The following example runs the command with the first ungrouping  phase
       for  small  user design hierarchies turned off and with changed setting
       for the second, delay-based automatic ungrouping phase.

         prompt> set compile_ultra_ungroup_small_hierarchies false
         prompt> set compile_auto_ungroup_delay_num_cells 300
         prompt> compile_ultra

SEE ALSO
       compile(2)