原创 Xilinx RLOC约束说明

RLOC Description
RLOC is a basic mapping and placement constraint. It is also a synthesis constraint. Relative location (RLOC) constraints group logic elements into discrete sets and allow you to define the location of any element within the set relative to other elements in the set, regardless of eventual placement in the overall design.
根据上述描述，RLOC是对一个功能元件集合做位置约束，而元件集合的相对位置固定，相对于FPGA器件的位置可变。
The general syntax for assigning elements to relative locations is
RLOC=XmYn
where
。    m and n are the relative X-axis (left/right) value and the relative Y-axis (up/down) value, respectively
。    the X and Y numbers can be any positive or negative integer including zero

如图所示：
A、B、C、D集合的两种不同的相对位置约束
 

RLOC Sets
在进行RLOC相对位置约束时，需要把相关元件组成一个集合，可以使用U_SET把不同层次下的元件组成一个集合。

U_SET
U_SET constraints enable you to group into a single set design elements with attached RLOC constraints that are distributed throughout the design hierarchy. The letter U in the name U_SET indicates that the set is user-defined.
RLOC Applicable Elements
1.    Registers
2.    FMAP
3.    HMAP
4.    F5MAP
5.    CY4
6.    CY_MUX
7.    ROM
8.    RAM
9.    RAMS, RAMD
10.    BUFT (Can only be used if the associated RPM has an RLOC_ORIGIN that causes the RLOC values in the RPM to be changed to LOC values.)
11.    WAND primitives that do not have a DECODE constraint attached
12.    LUTs, F5MUX, F6MUX, MUXCY, XORCY, MULT_AND, SRL16, SRL16E, F7MUX (for Virtex-II and Virtex-II Pro only), F8MUX (for Virtex-II and Virtex-II Pro only)
13.    Block RAMs
14.    Multipliers
RLOC Propagation Rules
RLOC is a design element constraint and any attachment to a net is illegal. When attached to a design element, RLOC propagates to all applicable elements in the hierarchy beneath the design element.
RLOC只能对涉及的功能元件进行约束，对NET信号进行约束是错误的。
设计实例：
INST "*/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
INST "*/infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;
 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
INST "*/infrastructure_top0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain;
 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
INST "*/infrastructure_top0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain;

INST "*/infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
INST "*/infrastructure_top0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain;

l0，l1，l2，l3 组成集合delay_calibration_chain，且l0，l1在同一个Slice中，同l2，l3的Slice上下紧邻。