原创 Wishbone总线信号转化到Avalon总线信号

Wishbone => Avalon Wishbone Avalon Bus Description

cyc = chipselect indicates that a valid bus cycle is in progress

stb = !write_n or !read_n indicates a valid data transfer cycle

we = !write_n and read_n indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.

ack = !waitrequest indicates the termination of a normal bus cycle by slave device.

Avalon => Wishbone Avalon Bus Wishbone Description

chipselect = cyc indiates that slave device is selected.

write_n = !(stb and we) indicated that master requests to write to slave device.

read_n = !(stb and !we) indicated that master requests to read from slave device.

waitrequest = !ack indicates that slave requests that master wait.