原创 Those Tiny Little Vias can Cause Big Ground Bounce

Introduction

Lately, a number of field issues have arisen regarding excessive ground bounce from simultaneously switching outputs (SSOs) and simultaneously switching CLBs. The combined transient currents from the switching rely on bypassing networks to keep the ground bounce to less than +/- 100 mV (200 mV peak-to-peak) in order for the FPGA to provide the best performance -- and lowest jitter.

We have discovered that there is an insidious little contributor to this problem that is often overlooked: the vias in the printed circuit board.

Causes of Excessive Ground Bounce

The usual causes of large ground bounce are: exceeding the SSO guidelines outlined in the data sheet, inadequate or insufficient bypass capacitors, selection of the wrong type of bypass capacitor, or improper mounting geometry.

The SSO guidelines limit the number of simultaneously switching IOBs at a specific current level to a fixed number per power and ground pin pair. This guideline assumes that a 0603 surface mount capacitor exists for each power and ground pin pair. It also assumed that, when this guideline is used, there is +/- 100 mV of noise, or less than 200 mV peak-to-peak of ground bounce noise. At this level, performance should be adequate, and there should be no functional problems with the FPGA.

The layout of the bypass capacitors should follow the guidelines outlined on page 5 of Xilinx Application Note 623: "Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors". All capacitors have a small internal series inductance; increasing this series inductance reduces the effectiveness of the bypass capacitor. The SSO guidelines assume that best practices are being followed. Any increase in the inductance or reduction in the number of bypass capacitors must be matched by a reduction in the number of IOBs that are switching per power ground pin pair.

The guidelines also assume that the capacitors are 0603 or 0402-style surface mount X7R material capacitors, or the equivalent. Other materials can have up to 25% or more equivalent series resistance (ESR) at the frequencies of interest, which lessens their effectiveness.

The mounting of the bypass capacitors is also sometimes overlooked. If the capacitors are located far away from the device pins, the trace inductance affects the results. Copper planes are ~ 160 pH per square, so a distance of one inch indicates one square inch of copper, or 160 pH. Beyond this, the transmission line effect of being more than 1/40 of a wavelength away prevents the effective transfer of energy. Thus, locating the capacitors close to the power ground pins is mandatory. (See the above-mentioned application note for details.)

However, there is an additional major contributor that is often overlooked:

Vias

The days of 0.063" thick 4-layer printed circuit boards are almost over. Boards are now 0.093" or even 0.125" thick, and contain anywhere from 12 to 26 layers. The ever-increasing density of designs and packages has led to tighter design rules for printed circuit boards, with designers needing ever-smaller features in order to place-and-route their boards.

Vias that used to be 0.011" in diameter on a 0.0625" thick board are now approaching 0.008" in diameter in a 0.125" thick board. If we measure the distance from the bypass capacitor to the power plane, and from the ground plan to the bypass capacitor for a capacitor on the backside of the printed circuit board, it amounts to one via worth of series inductance. Similarly, the distance to and from the device is another via length.

The 0.011" short via's inductance is ~ 0.9 nH. The longer and thinner 0.008" cousin has an inductance of ~2.3 nH. This increases the ground bounce approximately 2.5 times! Suddenly, the expected 200 mV peak-to-peak voltage is 500 mV peak-to-peak.

A more insidious problem with longer, thinner, and more inductive vias is that they form a parallel LC tank circuit with a lower natural frequency. Given the larger values of inductance, the parallel resonance of the printed circuit board can now show a resonance at a lower frequency than expected, and the peak-to-peak voltage may be even larger due to the "pumping" of the resonant circuit that is formed by the inductance and the capacitances.

The parallel circuit is formed by the loop of package-to-PCB inductance, in series with the PCB-to-bypass-capacitor inductance, in parallel with the bypass capacitor, which is in series with the on-chip effective capacitance and package capacitance.

Solutions

Reducing the number of SSOs is usually not an option, and a 250% problem (i.e., if the jitter is two and one-half times too large) cannot be corrected by slower slew rates or by reducing the strength of the IOBs by one or two current drive levels.

Unfortunately, a redesign and re-layout of the printed circuit board is required. Larger diameter vias or multiple vias are the solution.

One successful trick is to move the number of times that the SSOs switch. If they are not simultaneous, then they do not add up! The fixed phase shift of the DCM in Virtex-II (TM) and Virtex-II Pro (TM) can be used to move some of the IOBs switching by -2, -1, +1 and +2 ns, such that the switching currents are spread out, and do not add.

In one case, the phase was changed by -2 Ns for all switching IOBs, which resulted in a working design. The ground bounce was unchanged. Because the switching transients occurred before the clock input to the IOB, no jitter resulted at the clock input buffer.

This is a great technique to use for reducing ground bounce once it is within the guidelines, but it should not be used to patch up a design that has excessive ground bounce -- the ground bounce shows up as bad Vol and might affect other devices in the system.

Jitter is introduced at the rise time of the clock signal at the input buffer. If the ground bounce occurs while the clock input signal rises, the input buffer interprets this change in ground reference as a change in time.

Summary

Inductance in the power distribution network is a major problem. One source of excessive inductance may be the vias in series with the Vcc decoupling capacitors and to the device itself.

- Larger diameter vias, or multiple vias may be required in thicker printed circuit boards.

- Using the proper bypass capacitor types and the proper layout of bypass capacitors is always necessary.

- Observing the SSO guidelines, and de-rating them for inadequate bypassing is required.

- Staggering internal clocks can sometimes provide a means of controlling SSOs and reducing ground bounce