原创 奇数和偶数分频器

偶数分频器VHDL代码

--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fredivn is
 GENERIC (N:integer:=8);
port (clk:in std_logic;
  outclk:out std_logic);
end fredivn;

architecture rtl of fredivn is
signal count:integer;
begin
process(clk)
begin
 if(clk'event and clk='1') then
 if(count=N-1)then       --计数周期
   count<=0;
 else
 
   count<=count+1;
  if count<(integer(N/2)) then------产生分频，占空比50%
   outclk<='0';
  else
   outclk<='1';
  end if;
 end if;
 end if;
end process;
end rtl;

奇数分频器VHDL代码（占空比50%）

--odd frequency division

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fredivn1 is
 GENERIC (N:integer:=15);
port (clk:in std_logic;
  outclk:out std_logic);
end fredivn1;

architecture rtl of fredivn1 is
signal count1,count2:integer;
signal q,outclk1,outclk2:std_logic;
begin
q<=outclk1 and outclk2;

outclk<=q xor outclk1;

process(clk)
begin
 if(clk'event and clk='1') then
 if(count1=N-1)then
   count1<=0;
 else
 
   count1<=count1+1;
  if count1<(integer(N/2)) then
   outclk1<='0';
  else
   outclk1<='1';
  end if;
 end if;
 end if;
end process;
process(clk)
begin
 if(clk'event and clk='0') then
 if(count2=N-1)then
   count2<=0;
 else
 
   count2<=count2+1;
  if count2<(integer(N/2)) then
   outclk2<='1';
  else
   outclk2<='0';
  end if;
 end if;
 end if;
end process;  
  
end rtl;