原创 LPM的使用

The following file, reggen.vhd, contains the Entity Declaration and Architecture Body for reggen, a parameterized register function. The Generic Clause defines the REG_WIDTH parameter.

下面的reggen.vhd文件包含了一个实体，一个结构体以及一个参数化的寄存器功能。generic子句定义了REG_WIDTH参数。

ENTITY reggen IS
GENERIC(REG_WIDTH : INTEGER);--------例化的时候照抄-------
PORT(
   d: IN STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0);
   clk : IN STD_LOGIC;
  q: OUT STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0));
END reggen;

ARCHITECTURE a OF reggen IS
BEGIN
 PROCESS
 BEGIN
    WAIT UNTIL clk = '1';
  q <= d;
 END PROCESS;
END a;

The following example, reg24gen.vhd, instantiates two copies of reggen, reg12a and reg12b. The Package Declaration specifies the value of the TOP_WIDTH constant as the integer 24; the HALF_WIDTH constant is half of TOP_WIDTH. In the Generic Map Aspect of each instance of reggen, the constant HALF_WIDTH is explicitly assigned as the value of the REG_WIDTH parameter, thereby creating two 12-bit registers.

下例reg24gen示例了reggen的两个拷贝reg12a＆reg12b。包声明详细指定了TOP_WIDTH 常量为 integer 24;HALF_WIDTH常量是TOP_WIDTH 的一半。在属性映射里，the constant HALF_WIDTH 明确的被分配为参数REG_WIDTH 的值，因此创建了两个12位的寄存器。

PACKAGE reg24gen_package IS
CONSTANT TOP_WIDTH : INTEGER := 24; ---理解位C语言里的define吧，哈哈
CONSTANT HALF_WIDTH : INTEGER := TOP_WIDTH / 2;
END reg24gen_package;

USE work.reg24gen_package.ALL;

ENTITY reg24gen IS
PORT(
        d : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
        clk : IN STD_LOGIC;
        q: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END reg24gen;

ARCHITECTURE a OF reg24gen IS
    COMPONENT reggen
 GENERIC( REG_WIDTH : INTEGER);
  PORT(d : IN STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0);
             clk : IN STD_LOGIC;
             q : OUT STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0));
    END COMPONENT;
BEGIN 
 reg12a : reggen
               GENERIC MAP (REG_WIDTH => HALF_WIDTH)
               PORT MAP (d => d(HALF_WIDTH - 1 DOWNTO 0), clk => clk,
                         q => q(HALF_WIDTH - 1 DOWNTO  0));
       
 reg12b : reggen
  GENERIC MAP (REG_WIDTH => HALF_WIDTH)
         PORT MAP (d => d(HALF_WIDTH*2 - 1 DOWNTO HALF_WIDTH),
                  clk => clk,  q => q(HALF_WIDTH * 2 - 1 DOWNTO HALF_WIDTH));
END a;