原创 FDDRRSE

FDDRRSE

FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). It also has synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during any Low-to-High clock transition (C0 or C1). (Reset has precedence over Set.) When the S input is High and R is Low, the flip-flop is set, output High, during a Low-to-High clock transition (C0 or C1). Data on the D0 input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High C1 clock transition.

The flip-flop is asynchronously cleared, output Low, when power is applied.

Use the INIT attribute to initialize FDDRRSE during configuration.

Inputs							Outputs
C0	C1	CE	D0	D1	R	S	Q
	X	X	X	X	1	0	0
	X	X	X	X	0	1	1
	X	X	X	X	1	1	0
X		X	X	X	1	0	0
X		X	X	X	0	1	1
X		X	X	X	1	1	0
X	X	0	X	X	0	0	No Chg
	X	1	D0	X	0	0	D0
X		1	X	D1	0	0	D1

Usage

For HDL, this design element is instantiated rather than inferred.

FDDRRSE 模块有一个复位输入R ,一个置位输入S ,一个时钟使能输入CE ,两组数据和时钟对D0
与C0 和D1 与C1 ,一个数据输出Q。复位输入R ,当它为高的时候,重载所有的输入,并在时钟(C0 或者C1) 从低到高的过程中,将Q 的输出置为低(复位的优先级比置位的优先级要高) 。当S 的输入是高而R 的输入是低的时候,触发器被置位,在时钟(C0 或者C1) 从低到高的时候输出高电平。当R 和S 为低,CE 为高,C0 时钟从低到高的时候D0 上的数据加载到D 触发器中。当R 和S 为低,CE 为高,C1 时钟从低到高的时候D1 上的数据加载到D 触发器中。

VHDL Instantiation Template

Verilog Instantiation Template