原创 带CRC的移位寄存器

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity send is

PORT(clk    : in  std_logic;
     EN     : in  std_logic;
     input  : in std_logic_vector(7 downto 0);
     output : out std_logic);
end entity send;

architecture bhv of send is
 signal buff   :  std_logic_vector(7 downto 0);
 signal cout   :  std_logic_vector(3 downto 0);
 signal crc    :  std_logic;
 begin
 process(clk,input)
 begin

  if clk'event and clk='1'  then
   if EN='1'then
    buff<=input;
    cout<="0001";
    output<='0';
   elsif cout/="0000" then
    if cout<"1001" then
     cout<=cout+1;
     output<=buff(0);
      if buff(0)='1' then
      crc<= NOT crc;
      end if;
     buff(6 downto 0) <= buff(7 downto 1);
    elsif cout="1001" then
     cout<="0000";
     output<=crc;
    end if;
   else
    cout<="0000";
    crc<='0';
    output<='1';
   end if;
     end if;
 end process;
end bhv;