原创 基于分布式算法的fir设计

本人的eda课程设计，希望对大家有帮助。

其中包含matlab的仿真

modelsim的仿真

以及vhdl代码以及测试文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fir is
 port(
  --input
  clk,rst:in std_logic;
  fir_in:in std_logic_vector(11 downto 0);
  --output
  fir_out:out std_logic_vector(26 downto 0)
  );
end fir;

architecture rtl of fir is
  --定义12位的fir_in_reg
  signal fir_in_reg: std_logic_vector(11 downto 0);
  --定义13位的shift_buf 的8个数组
  subtype bit13 is std_logic_vector(12 downto 0);
  type z8 is array(0 to 7) of bit13; --type z8 is array(0 to 7) of std_logic_vector(12 downto 0);可以吗？？？？？？？？？？？？
  signal shift_buf: z8;
  --定义13位的加法寄存器 4个数组
  type add4 is array(0 to 3) of bit13;
  signal add_buf: add4;
  --定义13位的移位reg 4个数组
  type shift4 is array(0 to 3) of bit13;
  signal state_shift_buf: shift4;
  --用于LUT的输入(4位)
  signal table_4b: std_logic_vector(3 downto 0);
  --LUT的输出（12位）
  signal table_out_12b: std_logic_vector(11 downto 0);
  --sum(27位)
  signal sum: std_logic_vector(26 downto 0);
  --用于控制的信号
  signal divfre_count_4b: std_logic_vector(3 downto 0);
  signal clk_13: std_logic;
  signal state_reg: std_logic;
  --lut相关的信号
  signal sign_ex: std_logic_vector(26 downto 0);
  --与除2器有关信号
  signal delta_in: std_logic_vector(3 downto 0);
  signal delta_out: std_logic_vector(26 downto 0);
 begin
  --divfre_count_4b与clk_13寄存器
  process(clk,rst)
  begin
  if(rst='1') then
   divfre_count_4b<="0000";
   clk_13<='0';
  elsif(clk'event and clk='1') then
   if(divfre_count_4b="1101") then
    divfre_count_4b<="0000";
    clk_13<='1';
   else    
    divfre_count_4b<=divfre_count_4b+'1';
    clk_13<='0';
   end if;
  end if;
  end process;
  --数据输入寄存器 fir_in_reg 12位
  process(clk,rst,fir_in)
  begin
  if(rst='1') then
   fir_in_reg<="000000000000";
  elsif(clk'event and clk='1') then
   if(clk_13='1') then
   fir_in_reg<=fir_in;
   end if;
  end if;
  end process;
  --13位宽的shift_buf 的8个数组
  process(clk,rst,fir_in_reg)
  begin
  if(rst='1') then
   for i in 0 to 7 loop    
    shift_buf(i)<="0000000000000";
   end loop;
  elsif(clk'event and clk='1') then
   if(clk_13='1') then
   for i in 0 to 6 loop    
    shift_buf(i+1)<=shift_buf(i);
   end loop;
   shift_buf(0)(11 downto 0)<=fir_in_reg;
   shift_buf(0)(12)<=fir_in_reg(11);
   end if;
  end if;
  end process;
  --add_buf:13位宽 4个数组
  process(clk,rst,shift_buf)
  begin
  if(rst='1') then
   for i in 0 to 3 loop    
    add_buf(i)<="0000000000000";
   end loop;
  elsif(clk'event and clk='1') then
   if(clk_13='1') then
   for i in 0 to 3 loop
    add_buf(i)<=shift_buf(i)+shift_buf(7-i);--对称系数，相加。
   end loop;
   end if;
  end if;
  end process;
  --state_shift_buf 13位宽，4个数组
  process(clk,rst,add_buf)
  begin
  if(rst='1') then
   for i in 0 to 3 loop    
    state_shift_buf(i)<="0000000000000";
   end loop;
   state_reg<='0';
  elsif(clk'event and clk='1') then
   case state_reg is 
    when '0'=>
     for i in 0 to 3 loop
      state_shift_buf(i)<=add_buf(i);
     end loop;
     state_reg<='1';
    when '1'=>
     if(divfre_count_4b="1101") then
      state_reg<='0';
     else
      for i in 0 to 11 loop    
       --实现了四个12位移位寄存器（13位是符号为，不参与移位）
       state_shift_buf(0)(i)<=state_shift_buf(0)(i+1);
       state_shift_buf(1)(i)<=state_shift_buf(1)(i+1);
       state_shift_buf(2)(i)<=state_shift_buf(2)(i+1);
       state_shift_buf(3)(i)<=state_shift_buf(3)(i+1);
      end loop;
      state_reg<='1';
     end if;
    when others=>  
   end case;
  end if;
  end process; 
  --table_4b,LUT输入
  table_4b(0)<=state_shift_buf(0)(0);
  table_4b(1)<=state_shift_buf(1)(0);
  table_4b(2)<=state_shift_buf(2)(0);
  table_4b(3)<=state_shift_buf(3)(0);
  --LUT完成固定系数的乘法器
  process(table_4b)
  begin
   case table_4b is
    when "0000"=>table_out_12b<="000000000000";
    when "0001"=>table_out_12b<="000000101001";--41
    when "0010"=>table_out_12b<="000010000100";--132
    when "0011"=>table_out_12b<="000010101101";--173
    when "0100"=>table_out_12b<="000101010101";--341
    when "0101"=>table_out_12b<="000101111110";--382
    when "0110"=>table_out_12b<="000111011001";--473
    when "0111"=>table_out_12b<="001000000010";--514
    when "1000"=>table_out_12b<="001111111110";--514
    when "1001"=>table_out_12b<="001000100111";--551
    when "1010"=>table_out_12b<="001010000010";--642
    when "1011"=>table_out_12b<="001010101011";--683
    when "1100"=>table_out_12b<="001101010011";--851
    when "1101"=>table_out_12b<="001101111100";--892
    when "1110"=>table_out_12b<="001111010111";--983
    when "1111"=>table_out_12b<="010000000000";--1024
    when others=>table_out_12b<="000000000000";
   end case;
   end process;
  --sign_ex的26到12位等于table_out_12b(11)；以后的位等于table_out_12b;
  sign_ex(26)<=table_out_12b(11);
  sign_ex(25)<=table_out_12b(11);
  sign_ex(24)<=table_out_12b(11);
  sign_ex(23)<=table_out_12b(11);
  sign_ex(22)<=table_out_12b(11);
  sign_ex(21)<=table_out_12b(11);
  sign_ex(20)<=table_out_12b(11);
  sign_ex(19)<=table_out_12b(11);
  sign_ex(18)<=table_out_12b(11);
  sign_ex(17)<=table_out_12b(11);
  sign_ex(16)<=table_out_12b(11);
  sign_ex(15)<=table_out_12b(11);
  sign_ex(14)<=table_out_12b(11);
  sign_ex(13)<=table_out_12b(11);
  sign_ex(12)<=table_out_12b(11);
  sign_ex(11 downto 0)<=table_out_12b;
  --除2组合电路
  delta_in<=divfre_count_4b-"0001";
  with delta_in select
   delta_out<= sign_ex   when "0000",
              sign_ex(25 downto 0)&'0'  when "0001",
              sign_ex(24 downto 0)&"00"  when "0010",
             sign_ex(23 downto 0)&"000"  when "0011",
             sign_ex(22 downto 0)&"0000"  when "0100",
             sign_ex(21 downto 0)&"00000"  when "0101",
             sign_ex(20 downto 0)&"000000"  when "0110",
             sign_ex(19 downto 0)&"0000000"  when "0111",
             sign_ex(18 downto 0)&"00000000"  when "1000",
             sign_ex(17 downto 0)&"000000000"  when "1001",
             sign_ex(16 downto 0)&"0000000000"  when "1010",
             sign_ex(15 downto 0)&"00000000000"  when "1011",
             sign_ex(14 downto 0)&"000000000000"  when "1100",
             sign_ex(13 downto 0)&"0000000000000"  when "1101",
             sign_ex(12 downto 0)&"00000000000000"  when "1110",
             sign_ex(11 downto 0)&"000000000000000"  when "1111",
             sign_ex  when others;
  --sum 27位
  process(clk,rst,delta_out)
  begin
  if(rst='1') then
   sum<="000000000000000000000000000";
  elsif(clk'event and clk='1') then
   if(divfre_count_4b="0000") then
    sum<="000000000000000000000000000";
   elsif(divfre_count_4b="1101") then
    sum<=sum-delta_out;
   else
    sum<=sum+delta_out;
   end if;
  end if;
  end process;
  --27位输出寄存器
  process(clk,rst,sum)
  begin
  if(rst='1') then
   fir_out<="000000000000000000000000000";
  elsif(clk'event and clk='1') then
   if(divfre_count_4b="0000") then
    fir_out<=sum;
   end if;
  end if;
  end process;
 end rtl;

测试代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;

entity fir_tb is
generic (
 DEPTH : integer := 4096;-- ROM depth
 ROMFILE : string := "D:\pro\MOD\fir\OLDLEE.HEX";
 INFILE : string := "D:\pro\edaks\mod\input.txt";
 OUTFILE : string := "D:\pro\edaks\mod\OUTPUT.txt"
);
end fir_tb;
architecture rtl of fir_tb is
component fir port(
  clk,rst:in std_logic;
  fir_in:in std_logic_vector(11 downto 0);
  fir_out:out std_logic_vector(26 downto 0)
  );
end component;

 --dr_input
 signal dr_fir_in: std_logic_vector(11 downto 0) :="000000000000" ;
 signal dr_clk: std_logic :='0' ;
 signal dr_rst: std_logic :='1' ;
 signal dr_clk_14: std_logic :='0' ;
 --output
 signal dr_fir_out: std_logic_vector(26 downto 0);
 --type TEXT is file of string;
 file     input   : text is out INFILE;
 file     output   : text is out OUTFILE;
 type memory is array (0 to DEPTH-1) of std_logic_vector(7 downto 0);
 signal store:  memory;
 signal initialized: boolean := false;
 signal count: std_logic_vector(11 downto 0);

 -- Converts std_logic_vector to natural
 function to_nat (input : std_logic_vector) return natural is
  variable result : natural;
  variable weight : natural;
 begin
  result:=0;
  weight:=1;
  for i in input'LOW to input'HIGH loop
   if (input(i)='1' or input(i)='H') then
    result := result + weight;
   end if;
   weight := weight * 2;
  end loop;
  return result;
 end to_nat;
 
 -- Converts hexadecimal string to natural
 function to_nat (input : string) return natural is
  variable result : natural;
 begin
  result:=0;
  for i in input'LEFT to input'RIGHT loop
   result := result * 16;
   case input(i) is
    when '0'      => result := result + 0;
    when '1'      => result := result + 1;
    when '2'      => result := result + 2;
    when '3'      => result := result + 3;
    when '4'      => result := result + 4;
    when '5'      => result := result + 5;
    when '6'      => result := result + 6;
    when '7'      => result := result + 7;
    when '8'      => result := result + 8;
    when '9'      => result := result + 9;
    when 'A'      => result := result + 10;
    when 'B'      => result := result + 11;
    when 'C'      => result := result + 12;
    when 'D'      => result := result + 13;
    when 'E'      => result := result + 14;
    when 'F'      => result := result + 15;
    when others   => null;
   end case;
  end loop;
  return result;
 end to_nat;
 
 -- Converts hexadecimal string to binary vector
 function to_std_logic_vector (input : string)
  return std_logic_vector is
  variable result : std_logic_vector(0 to 4*input'LENGTH-1);
 begin
  result := (others => '0');
  for i in input'LEFT to input'RIGHT loop
   case input(i) is
    when '0'      => result((i-1)*4 to 3+(i-1)*4):="0000";
    when '1'      => result((i-1)*4 to 3+(i-1)*4):="0001";
    when '2'      => result((i-1)*4 to 3+(i-1)*4):="0010";
    when '3'      => result((i-1)*4 to 3+(i-1)*4):="0011";
    when '4'      => result((i-1)*4 to 3+(i-1)*4):="0100";
    when '5'      => result((i-1)*4 to 3+(i-1)*4):="0101";
    when '6'      => result((i-1)*4 to 3+(i-1)*4):="0110";
    when '7'      => result((i-1)*4 to 3+(i-1)*4):="0111";
    when '8'      => result((i-1)*4 to 3+(i-1)*4):="1000";
    when '9'      => result((i-1)*4 to 3+(i-1)*4):="1001";
    when 'A'      => result((i-1)*4 to 3+(i-1)*4):="1010";
    when 'B'      => result((i-1)*4 to 3+(i-1)*4):="1011";
    when 'C'      => result((i-1)*4 to 3+(i-1)*4):="1100";
    when 'D'      => result((i-1)*4 to 3+(i-1)*4):="1101";
    when 'E'      => result((i-1)*4 to 3+(i-1)*4):="1110";
    when 'F'      => result((i-1)*4 to 3+(i-1)*4):="1111";
    when others   => null;
   end case;
  end loop;
  return result;
 end to_std_logic_vector;

 -- Initializing memory contents :
 function initmem return memory is
  file     source   : text is in ROMFILE;
  variable row      : line;
  variable char     : character;
  variable addr     : string(1 to 4);
  variable data     : string(1 to 2);
  variable data1    : string(1 to 2);
  variable number   : natural;
  variable address  : natural;
  variable checksum : natural;
  variable sum      : natural;
  variable vector   : std_logic_vector(7 downto 0);
  variable mem      : memory;
 begin
  for i in mem'range loop
   mem(i) := (others => '0');
  end loop;
  while not endfile(source) loop
   readline(source, row);
   if row'LENGTH>1 and row(1)=':' then
    READ(row, char);
    READ(row, data);
    number:=to_nat(data);
    sum      :=number;
    READ(row, data);
    checksum :=to_nat(data);
    sum      :=(sum+checksum) mod 256;
    READ(row, data1);
    checksum :=to_nat(data1);
    sum      :=(sum+checksum) mod 256;
    addr     :=data & data1;
    address  :=to_nat(addr);
    READ(row, data);
    checksum :=to_nat(data);
    sum      :=(sum+checksum) mod 256;
    while number>0 loop
     READ(row, data);
     vector   :=to_std_logic_vector(data);
     checksum :=to_nat(data);
     sum      :=(sum+checksum) mod 256;
     mem(address) := vector;
     address  :=address+1;
     number   :=number-1;
    end loop;
    READ(row, data);
    checksum :=to_nat(data);
    sum      :=(sum+checksum) mod 256;
    assert (sum=0)
     report "Invalid check sum" &
     " in the program memory init file."
     severity error;
   end if;
  end loop;
  return mem;
 end initmem;

begin
 fir1: fir port map(clk=>dr_clk,rst=>dr_rst,fir_in=>dr_fir_in,fir_out=>dr_fir_out);
 process(dr_clk)
 begin
  dr_clk<=not dr_clk after 10 ns;
 end process;
 process(dr_clk_14)
 begin
  dr_clk_14<=not dr_clk_14 after 140 ns;
 end process;
 process
 begin
 dr_rst<='0' after 25 ns;
 wait;
 end process;

 --init_rom_proc :
 process
  variable storevar : memory;
 begin
  if not initialized then
   storevar := initmem;
   initialized <= true;
  end if;
  store <= storevar;
  wait ; -- wait forever ...
 end process;

 read_rom_proc :
 process (dr_clk_14)
  variable count : integer :=0;
  variable doutvar : std_logic_vector(7 downto 0);
 begin
  if (dr_clk_14'event and dr_clk_14 = '1') then
    if(count=4096) then
    else
   doutvar := store(count);
   count:=count+1;
   end if;
  end if;
  dr_fir_in <= '0'&'0'&'0'&'0'&doutvar;
 end process;
 process (dr_clk_14)
 variable inline : LINE;
 variable outline : LINE;
 variable outdata : integer :=0;
 variable indata : integer :=0;
 begin
  if (dr_clk_14'event and dr_clk_14 = '1') then
    outdata :=CONV_INTEGER(dr_fir_out);
    indata:=CONV_INTEGER(dr_fir_in);
   write(outline,outdata);
   write(outline,string'(" "));
   write(inline,indata);
   write(inline,string'(" ")); 
    writeline(input,inline);
    writeline(output,outline);   
  end if;
 end process;
end rtl;

matlab

in=[
....];
out=[
....];
out=out/2048;
t0=0:length(in)-1;
t1=0:length(out)-1;
plot(t0, in, '-r', t1, out, ':b');%'-r'表示红色线；':b'表示虚蓝线
title('输入输出信号的时域曲线 红色线表示输入 蓝色线表示输出');
xlabel('t');
ylabel('abs');
axis([0,4096,0,max(max(in),max(out))]);

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
fin=fft(in);
fout=fft(out);
ft0=0:length(fin)-1;
ft1=0:length(fout)-1;
fabs=abs(fin);
f_in_abs=abs(fin);
f_out_abs=abs(fout);
%plot(ft0,f_in_abs);%
%plot(ft1,f_out_abs);%
plot(ft0,f_in_abs, '-r',ft1,f_out_abs, ':b');%'-r'表示红色线；':b'表示虚蓝线
title('输入输出信号的频域曲线 红色线表示输入 蓝色线表示输出');
xlabel('f');
ylabel('abs');

测试文件读入的hex文件

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