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原创跨时钟域设计的一点总结（2）

 2013-9-3 00:19  2598 21 21 分类: FPGA/CPLD

附录（相关设计技巧）：

1. 慢时钟域到快时钟域的同步及上升（下降）沿检测电路

同步和上升沿检测电路：（注意输入B是被反向过的）

时序图：

代码实现为：先将发送时钟域过来的信号用寄存器打两拍，然后将输出信号A和再打一拍的反向信号B相与（如果是下降沿检测，则将输出信号A反向和再打一拍的同向信号B相与）。

拓展：如果将先将发送时钟域过来的信号用寄存器打两拍，然后将输出信号A和再打一拍的信号B相一或，就得到的是上升沿和下降沿都检测的逻辑。

2. 脉冲检测（将脉冲信号转换为电平信号，pulse-toggle-circuit）

基本电路为：

时序图：

代码实现为：

always@(posedge clk1 or negedge nrst)

begin

if(!nrst)

Q <= 0;

else

Q <= D;

end

assign D = Data ? Q_bar : Q;

拓展：。。。

3. 完整握手流程

完整握手流程为：

时序图：

代码实现为：

4. 部分握手流程I（完整握手流程的简化版）

部分握手流程I为：

时序图：

说明：省去了完整握手流程里面的最后一步，也就是ACK信号自动会把自己de-assert，而不是要等检测到REQ信号de-assert之后了。

In the first partial handshake scheme, Circuit A asserts its request signal and the Circuit B acknowledges it with a single clock-wide pulse. In this case, Circuit B does not care when Circuit A drops its request signal. However, to make this technique work, Circuit A must drop its request signal for at least one clock cycle otherwise Circuit B cannot distinguish between the previous and the new request.（A发出的REQ信号必须至少无效持续一个时钟周期，否则B无法辨别两个响铃的REQ信号）

With this handshake, Circuit B uses a level synchronizer for the request signal and Circuit A uses a pulse synchronizer for the acknowledge signal. In this handshake protocol the acknowledge pulses only occur when Circuit B detects the request signal. This allows Circuit A to control the spacing of the pulses into the synchronizer by controlling the timing of its request signal.

5. 部分握手流程II（完整握手流程的简化版）

部分握手流程II为：

时序图：

说明：省去了完整握手流程里面的最后两步，两个信号在assert保持一段时间以后都是自动de-assert，不在相互检测。

In this second partial handshake scheme, Circuit A asserts it request with a single clock-wide pulse and Circuit B acknowledges it with a single clock-wide pulse. In this case, both circuits need to save state to indicate that the request is pending.

This type of handshake uses pulse synchronizers but if one circuit has a clock that is twice as fast as the other, that circuit can use an edge-detect synchronizer instead. （如果有一个时钟域的时钟比另外一个时钟域的时钟快两倍以上，则可以使用边沿检测同步电路来代替握手电路）

6. Basic Data Path Design

基本电路为：

时序图：

说明：A design using full handshake signaling has a large window of time for the receiving circuit to sample the signal bus and is not very efficient. The same design can use a partial handshake instead of the full handshake to speed up the transfer.

7. Advanced Data Path Design

基本电路为：

时序图：

代码实现为：

跨时钟域