原创 xilinx GSR

excerpt from http://forums.xilinx.com/t5/Archived-ISE-issues/FPGA-Power-On-Reset/m-p/7027?query.id=134602

Initialization values from INIT statements are downloaded to the part in the bitstream.Since this is a serial process, registers are initialized at different times throughout the configuration process, but since the logic is not active yet you can consider this happening before "global reset".

GSR is not an asynchronous reset/preset signal in the hardware.  Think of it as the signal that holds everything quiescent during configuration and for a programmable number of configuration clocks thereafter.

When GSR goes inactive, which happens exactly once after configuration, the whole FPGA is allowed to run as programmed.  This is the edge that can cause issues in any synchronous systems which require multiple flip-flops to start on the same clock edge.  The first issue stems from the configuration clock being asynchronous (in most cases) from the clock to the state logic.  The second issue is the large skew in the GSR net to various parts of the FPGA.

A simple method for a "power-on" reset with synchronous release is to instantiate a series of D flip-flops as a shift register.  For active high reset these would be FDP flip-flops, which are initialized to 1 if their preset input is asserted.  The actual preset input can be tied low (inactive) if you don't need to re-assert reset.  The input to the shift register would be tied low, so after a few clocks the output will synchronously go low.  The point of using more than one flip-flop is to give enough time for all state machine flip-flops to be out of global set/reset.  I typically use three flip-flops for this.

Flip-flops in the Xilinx FPGA's all have a reset input that can be configured as synchronous or asynchronous.  It can also be configured to reset low or high (preset).  This is independent of the INIT value of the flip-flop, however if not otherwise specified, the INIT value will match the reset state.  In this default case you also don't need to do anything special for simulation, as long as you drive the asynchronous (or synchronous) reset input to you machine at the start of simulation.  GSR is driven for 100 nS by default in simulation for library elements.

excerpt from http://forums.xilinx.com/t5/Design-Entry/How-to-use-GSR/m-p/100256#M1657

A GSR is an ASIC technique that is not required in FPGAs. It went away as it was terrribly slow. Avoid connecting a signal to the GSR startup block.  In summary, the solution is that routing is fairly plentyful in an FPGA so just code normally and use local routing to route your reset.