因为这次做的频率检测系统中，用到了高频时钟输入，一直也想把PLL的输出搞清楚，今天就拿一个简单的程序，自己分析下，实验室有3块板子，因为用EP<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />1C3T144C8N比较多，而且做这个系统用的也是这块板子。
直奔主题吧，先来看看EP1C3T144的管脚图
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我用红色箭头标示的就是EP1C3T144C8上所有跟CLK和PLL有关系的管脚，这是我从
Altea官方文档上面取出来的信息
Bank Number VREF Bank Pin Name/Function Optional Function(s) T144
B1 VREF0B1 IO LVDS3p /CLKUSR pin 3
B1 VREF2B1 IO DPCLK0 pin 28
B1 VREF0B1 IO DPCLK1 pin 10
B2 VREF2B2 IO DPCLK2 pin 134
B2 VREF0B2 IO DPCLK3 pin 119
B3 VREF0B3 IO DPCLK4 pin 100
B3 VREF2B3 IO DPCLK5 pin 82
B4 VREF0B4 IO DPCLK6 pin 62
B4 VREF2B4 IO DPCLK7 pin 47
VREF1B1 VCCA_PLL1 pin 15
VREF1B1 GNDA_PLL1 pin 18
VREF1B1 GNDG_PLL1 pin 19
B1 VREF1B1 CLK0 LVDSCLK1p pin 16
B1 VREF1B1 CLK1 LVDSCLK1n pin 17
B3 VREF1B3 CLK2 LVDSCLK2p pin 93
B3 VREF1B3 CLK3 LVDSCLK2n pin 92
B1 VREF1B1 DCLK DCLK pin 24
B1 VREF1B1 IO PLL1_OUTp pin 26
B1 VREF1B1 IO PLL1_OUTn pin 27
注： LVDS：Low-Voltage Differential Signaling 低压差分信号
Pin Information for the Cyclone? EP1C3T144 Device
下面是管脚的信息：
Pin Name Pin Type (1st, 2nd, &3rd Function)
CLKUSR I/O，Input
Pin Description
Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration.
用户可选的时钟输入。同步一个或多个芯片的初始化（配置）。在配置完成后这个管脚可以当做普通的I/O口。
Pin Name Pin Type (1st, 2nd, &3rd Function)
DPCLK[7..0] I/O
Pin Description
Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins.
2种功能的时钟管脚，这些管脚都被连接到全局时钟网络。既可以用于高扇出的控制信号，如时钟，清零，IRDY, TRDY, or DQS等信号，还可以当做普通的I/O口。
Pin Name Pin Type (1st, 2nd, &3rd Function)
VCCA_PLL[1..2] Power
Pin Description
Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used.
锁相环的模拟电源。此管脚必须连接到1.5V的模拟电压，即使锁相环没有用到。
Pin Name Pin Type (1st, 2nd, &3rd Function)
GNDA_PLL[1..2] Ground
Pin Description
Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board.
锁相环的模拟地。此管脚可以连接到板子上的地层。
Pin Name Pin Type (1st, 2nd, &3rd Function)
GNDG_PLL[1..2] Ground
Pin Description
Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board.
锁相环的防护环式地层，此管脚可以连接到板子上的地层。（这个涉及到IC设计的专业知识，我也不清楚 防护环式地层 是什么意思）。
Pin Name Pin Type (1st, 2nd, &3rd Function)
CLK0 Input, LVDS Input
Pin Description
Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1.
专用的全局输入时钟。这个管脚还有个功能就是当做LVDSCLK1p，即给PLL输入不同频率的时钟。
LVDSCLK1p ：Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK0 input pin
LVDSCLK1p：第二个功能就是当做PLL的时钟输入，如果PLL不需要不同频率的时钟输入的话，这个管脚就是全局输入时钟。
这个功能一般我们用不到，在Altera的文档中也有介绍，
Manual Clock Switchover
The Cyclone II PLLs support manual switchover of the reference clock through internal logic. This enables you to switch between two reference input clocks.
Cyclone II器件中的PLL支持通过内部的逻辑来控制切换 PLL1 的输入参考时钟，这样你可以在2个输入时钟中切换，仔细的朋友可能看到过。
Pin Name Pin Type (1st, 2nd, &3rd Function)
CLK1 Input, LVDS Input
Pin Description
Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. The EP1C3T100 does not support this clock pin.
专用的全局输入时钟。这个管脚还有个功能就是当做LVDSCLK1n，即给PLL1输入不同频率的时钟，但是
EP1C3T100芯片不支持这个时钟输入
Pin Name Pin Type (1st, 2nd, &3rd Function)
CLK2 Input, LVDS Input
Pin Description
Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2.
专用的全局输入时钟。这个管脚还有个功能就是当做LVDSCLK2p，即给PLL2输入不同频率的时钟。
Pin Name Pin Type (1st, 2nd, &3rd Function)
CLK3 Input, LVDS Input
Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. The EP1C3T100 does not support this clock pin.
专用的全局输入时钟。这个管脚还有个功能就是当做LVDSCLK2p，即给PLL2输入不同频率的时钟，但是
EP1C3T100芯片不支持这个时钟输入。
Pin Name Pin Type (1st, 2nd, &3rd Function)
DCLK Input (PS mode), Output (AS mode)
Pin Description
In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration.
在PS配置模式下，DCLK是用于将.sof文件数据下载到芯片内部sram里面的时钟，对FPGA芯片来说是输入时钟（控制下载速度），在AS配置模式下，DCLK是FPGA的输出时钟（也是控制下载速度），用于将.pof文件数据下载到外部串行配置芯片EPCS中。
Pin Name Pin Type (1st, 2nd, &3rd Function)
PLL1_OUTp I/O, Output
Pin Description
External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. The EP1C3T100 does not support this output pin.
PLL1输出给外部器件（如SDRAM）用的时钟，输出的时钟可以是差分或单端I/O标准。如果实例化PLL时，没有用到此时钟，这个管脚也可以当做普通的I/O口，EP1C3T100芯片不支持这个时钟输出
Pin Name Pin Type (1st, 2nd, &3rd Function)
PLL1_OUTn I/O, Output
Pin Description
Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin. The EP1C3T100 does not support this output pin.
PLL1输出给外部器件（如SDRAM）用的时钟的负端。如果输出时钟是单端信号，这个管脚也可以当做普通的I/O口。
分析完了，在来看看代码，声明有些复位处理是学习特权同学的方法。
module pll_100M (
clk,rst_n,
sys_rst_n,sdram_clk
);
input clk; //FPAG输入时钟信号20MHz
input rst_n; //FPGA输入复位信号
output sys_rst_n; //系统复位信号，低有效
output sdram_clk; //PLL输出100MHz时钟,送给外部SDRAM
wire locked; //PLL输出有效标志位，高表示PLL输出有效
wire clk_100M; //PLL输出100MHz时钟,内部用
//----------------------------------------------
//PLL复位信号产生，高有效
//异步复位，同步释放
wire pll_rst; //PLL复位信号，高有效
reg rst_reg1,rst_reg2;
always @(posedge clk or negedge rst_n)
if(!rst_n)
rst_reg1 <= 1'b1;
else
rst_reg1 <= 1'b0;
always @(posedge clk or negedge rst_n)
if(!rst_n)
rst_reg2 <= 1'b1;
else
rst_reg2 <= rst_reg1;
assign pll_rst = rst_reg2;
//----------------------------------------------
/*
rst_n 0 0 0 0 1 1 1 1 1
rst_reg1 1 1 1 1 0 0 0 0 0
rst_reg2 1 1 1 1 1 0 0 0 0 0
pll_rst 1 1 1 1 1 0 0 0 0 0
*/
//----------------------------------------------
//系统复位信号产生，低有效
//异步复位，同步释放
wire sys_rst_n; //系统复位信号，低有效
wire sysrst_nr0;
reg sysrst_nr1,sysrst_nr2;
assign sysrst_nr0 = rst_n & locked; //系统复位直到PLL有效输出
always @(posedge clk_100M or negedge sysrst_nr0)
if(!sysrst_nr0) sysrst_nr1 <= 1'b0;
else sysrst_nr1 <= 1'b1;
always @(posedge clk_100M or negedge sysrst_nr0)
if(!sysrst_nr0) sysrst_nr2 <= 1'b0;
else sysrst_nr2 <= sysrst_nr1;
assign sys_rst_n = sysrst_nr2;
//----------------------------------------------
/*
sysrst_nr0 0 0 0 1 1 1 1
sysrst_nr1 0 0 0 1 1 1 1
sysrst_nr2 0 0 0 0 1 1 1 1
sys_rst_n 0 0 0 0 1 1 1 1
*/
//----------------------------------------------
//例化PLL产生模块
pll_ctrl U1(
.areset(pll_rst), //PLL复位信号,高电平复位
.inclk0(clk), //PLL输入时钟，20MHz
.c0(clk_100M), //PLL输出100MHz时钟
.e0(sdram_clk), //PLL输出100MHz时钟，送给外部SDRAM
.locked(locked) //PLL输出有效标志位，高表示PLL输出有效
);
endmodule
如果分配管脚时，将sdram_clk分配到 pin 28 (DPCLK0)，走到布局布线时就会报错：
右键 点击 HELP ，我非常推荐大家在用Quartus时，遇到错误到HELP里面去找答案，这是最有效的解决方法。
Can't place <name> PLL "<name>" because I/O pin "<name>" (port type <name> of the PLL) is assigned to a location which is not connected to port type <name> of any PLL on the device
CAUSE: You assigned a pin to a location that is not connected to the specified port type of the specified fast PLL or enhanced PLL. The Fitter cannot place the PLL.
ACTION: Change the location assignment for the I/O pin or delete the assignment.
就是在分配管脚时，DPCLK这样的管脚不支持 输出高频的时钟，解决方法：重新分配适合的管脚。
如果分配管脚时，将sdram_clk分配到 pin 16 (CLK0)，就不可以，因为CLK0~CLK3 是输入时钟管脚。
如果分配管脚时，将sdram_clk分配到 pin 26 (PLL1_OUTp)，编译通过
如果分配管脚时，将sdram_clk分配到 pin 27 (PLL1_OUTn)，走到布局布线时还是会报错：
CAUSE: You selected a target device for the current project. However, the Fitter cannot place the specified fast PLL or enhanced PLL in the target device due to device constraints.
ACTION: Locate the source of the message to determine the nature of the error. Modify the design accordingly so that the Fitter can place the PLL. Click the + icon to expand this message in the Messages window or Messages section of the Report window to display details about why the Quartus II software did not place the PLL.
原因是器件不支持。
全文完。总结了这么多，嘿嘿，其实实验室板子上有一块SDRAM，当时学习了SDRAM好一段时间，最后上板子调试的时候分配sdram_clk管脚时，不能通过，当时也没有搞清楚为什么，现在清楚了。以后画板子的时候这点也需要注意下，为画板子打好基础吧，到时就当毕业设计咯。
文中有那里错误的地方欢迎大家指正，一起学习。翻译也可能有错误的地方，像这样的东西还是推荐大家看Altera官方原汁原味的文档，可以参考下我的分析。附件中有工程代码和EP1C3T144C8的管脚信息文档。
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用户383871 2011-9-14 10:17
用户1526653 2010-5-31 12:53
coyoo 2010-5-31 09:52