原创 The ERC for PLL in 40nm process

2011-6-14 13:46 3783 4 4 分类: 工程师职场

Today, I verified all of the project IPs and found the ERC error in the following:

For PLL(PLLTS40GINT), RULECHECK npvss49...............TOTAL Result Count=50 (50)

For PLL_CAP(CAPTS40LP100F),RULECHECK floating.psub..........TOTAL Result count=1(1)

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And checked all release note and document files, I have not found some explanations about those ERC errors.

Response from the PLL vendor

The npvss49 is flagged because the PLL uses the NMOSCAP_18 device for the loop filter. The device is an NMOS in n-well, and is good for high-Q, high density capacitors.The error is for nwell connected to ground, but it can be ignored in this case because it is expected for the drain/source of the NMOSCAP_18 to be connected to VSS. This error is only a problem in the case of a PMOS device(which we do not have here)

The floating .psub error is a chip level violation and should go away when you connect the p-substrate to ground. The PLL_CAP cell does not contain a substrate connection since it also users the NMOSCAP_18 device.

 

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