原创 Design of high performance QDR2/DDR2 RAM Controller on Stratix-IV FPGA

Abstract

This article introduced a data capturing technology which used on high performance QDR2 SSRAM、DDR2 SDRAM interface. This technology base on several primitives, such as DQS Delay Chain、Input Phase Alignment and Half-Rate Input. The PLLs’ dynamic phase shift function also been taken in to account.

Introduction

We focus on the physic layer especially the read data path of the interface because this is the difficult point of FPGA implement. Both of the QDR2 and DDR2 are source-synchronized interface. The clock and data is edge aligned at the read path. In this design, The first stage using DQS Delay Chain delayed source-synchronized clock ( dqs or cq) to scan the valid window of DQ. Then, derive the most appropriate delay value and apply it on DQS Delay Chain. The second stage using dynamic phase shifting re-synchronize clock to transfer the read data from source-synchronized clock domain to system clock domain. All of this use the I/O resource of Stratix-III/Stratix-IV, avoid complicated constraints.

The write data path

The write data path is somewhat simple, employ the DDIO_OUT primitive. The FPGA Clock in the figure is the 270 degree output of PLL. Feed the Write Data Rise with the MSB of parallel write data, and the Write Data Fall with LSB.

 


The main clock K/K# can be generated by the same method. Tie the Write Data Rise to ‘1’, the Write Data Fall to ‘0’ and the clock port using PLL out 0 degree clock.

The read data path

The read data path is different with the ALTERA IP Core and the block RAM not been used. Be fit for low latency and full rate circumstance.

The figure above shows the I/0 structure of StratixIII / StratixIV and the primitives been used.

1)     The DQS(CQ) capture the input data from pin and translate each double edge data to two bits single edge data. On the way from CQ pin to the clock port of DDIO_IN, the CQ delayed by DQS_DELAY_CHAIN but the figure doesn’t show it.

2)     The single edge data sampled by resync_clk in the Alignment_Synchronous Registers, and then enter the Half Data Rate Registers. The Resync_clk is the common source clock of the sys_clk and they have the same frequency.

3)     The Half_Data_Rate_Registers primitive been used but not its intrinsic function. All of the registers working at the same frequency as QDR2 SSRAM.

4)     The read data enter LUT configured selector once they get out of the I/O registers. The sysclk_phase_sel derived from the phase difference of resync_clk and sys_clk.