原创 verilog学习笔记——电子时钟

初学verilog，写的第一个程序——电子时钟，有很多不足，程序有待优化，还需请教大家。一起交流一起进步。

module clkseg(clk,rst,data,en);

input clk;
input rst;
output data;
output en;

reg [7:0] data;//段选
reg [7:0] en;//位选

reg [5:0] second;//秒
reg [5:0] minute;//分
reg [4:0] hour;//时

reg [7:0] sec_0;
reg [7:0] sec_1;
reg [7:0] min_0;
reg [7:0] min_1;
reg [7:0] hou_0;
reg [7:0] hou_1;

reg [9:0] count_1;//分频计数
reg [15:0] count_2;//分频计数

reg clk_1s;
reg clk_1ms;

reg [2:0] sel;

initial
begin
 count_1 <= 10'd0;
 count_2 <= 19'd0;
 second <= 6'd0;
 minute <= 6'd0;
 hour <= 5'd0;

end

always@(posedge clk or negedge rst)
begin
 if(!rst)
 begin
  count_1 <=0;
  count_2 <=0;
 end
 else if(count_2 <50000)
  count_2 <= count_2 + 1'b1;
 else
 begin
  count_2 <= 1'b0;
  clk_1ms <= ~ clk_1ms;
  count_1 <= count_1 + 1;
  if(count_1==500)
   begin
    clk_1s <= ~clk_1s;
    count_1 <= 0;
   end
 end
end

always@(posedge clk_1s or negedge rst)
begin
 if(!rst)
 begin
  second[5:0] <=6'b00_0000;
  minute[5:0] <= 6'b000000;
  hour[4:0] <= 6'b000000;
 end
 else
 begin
  second[5:0] <= second[5:0] + 1;
  if(second[5:2]==4'b1111)
  begin
   second[5:0] <=6'b00_0000;
   minute[5:0] <= minute[5:0] +1;
   if(minute[5:2]==4'b1111)
   begin
    minute[5:0] <= 6'b000000;
    hour[4:0] <= hour[4:0] +1;
    if(hour[4:3]==2'b11)
    begin
     hour[4:0] <= 6'b000000;
    end
   end
  end
 end
 
end

always@(posedge clk_1s)
begin

 case(second%10)
 4'd0:sec_0<=8'hc0;
 4'd1:sec_0<=8'hf9;
 4'd2:sec_0<=8'ha4;
 4'd3:sec_0<=8'hb0;
 4'd4:sec_0<=8'h99;
 4'd5:sec_0<=8'h92;
 4'd6:sec_0<=8'h82;
 4'd7:sec_0<=8'hf8;
 4'd8:sec_0<=8'h80;
 4'd9:sec_0<=8'h98;
 endcase

 case(second/10)
 4'd0:sec_1<=8'hc0;
 4'd1:sec_1<=8'hf9;
 4'd2:sec_1<=8'ha4;
 4'd3:sec_1<=8'hb0;
 4'd4:sec_1<=8'h99;
 4'd5:sec_1<=8'h92;
 4'd6:sec_1<=8'h82;
 4'd7:sec_1<=8'hf8;
 4'd8:sec_1<=8'h80;
 4'd9:sec_1<=8'h98;
 endcase

 case(minute%10)
 4'd0:min_0<=8'hc0;
 4'd1:min_0<=8'hf9;
 4'd2:min_0<=8'ha4;
 4'd3:min_0<=8'hb0;
 4'd4:min_0<=8'h99;
 4'd5:min_0<=8'h92;
 4'd6:min_0<=8'h82;
 4'd7:min_0<=8'hf8;
 4'd8:min_0<=8'h80;
 4'd9:min_0<=8'h98;
 endcase

 case(minute/10)
 4'd0:min_1<=8'hc0;
 4'd1:min_1<=8'hf9;
 4'd2:min_1<=8'ha4;
 4'd3:min_1<=8'hb0;
 4'd4:min_1<=8'h99;
 4'd5:min_1<=8'h92;
 4'd6:min_1<=8'h82;
 4'd7:min_1<=8'hf8;
 4'd8:min_1<=8'h80;
 4'd9:min_1<=8'h98;
 endcase

 case(hour%10)
 4'd0:hou_0<=8'hc0;
 4'd1:hou_0<=8'hf9;
 4'd2:hou_0<=8'ha4;
 4'd3:hou_0<=8'hb0;
 4'd4:hou_0<=8'h99;
 4'd5:hou_0<=8'h92;
 4'd6:hou_0<=8'h82;
 4'd7:hou_0<=8'hf8;
 4'd8:hou_0<=8'h80;
 4'd9:hou_0<=8'h98;
 endcase

 case(hour/10)
 4'd0:hou_1<=8'hc0;
 4'd1:hou_1<=8'hf9;
 4'd2:hou_1<=8'ha4;
 4'd3:hou_1<=8'hb0;
 4'd4:hou_1<=8'h99;
 4'd5:hou_1<=8'h92;
 4'd6:hou_1<=8'h82;
 4'd7:hou_1<=8'hf8;
 4'd8:hou_1<=8'h80;
 4'd9:hou_1<=8'h98;
 endcase
 
end

always @(posedge clk_1ms or negedge rst)
begin
 if(!rst)
  en <= 8'b0000_0000;
 else if(sel<8)
  sel <= sel + 1'b1;
 else
  sel <= 3'b000;
  
 begin
   case(sel)
       3'b000 :
          data <= hou_1;
       3'b001 :
          data <= hou_0;
       3'b010 :
          data <= 8'b1011_1111;
       3'b011 :
          data <= min_1;
       3'b100 :
          data <= min_0;
       3'b101 :
          data <= 8'b1011_1111;
       3'b110 :
          data <= sec_1;
       3'b111 :
          data <= sec_0;
    endcase
    end
   
 begin
   case(sel)
       3'b000 :
          en <= 8'b1111_1110;
       3'b001 :
          en <= 8'b1111_1101;
       3'b010 :
          en <= 8'b1111_1011;
       3'b011 :
          en <= 8'b1111_0111;
       3'b100 :
          en <= 8'b1110_1111;
       3'b101 :
          en <= 8'b1101_1111;
       3'b110 :
          en <= 8'b1011_1111;
       3'b111 :
          en <= 8'b0111_1111;
    endcase
    end
end

endmodule