原创 【转】电地完整性、信号完整性分析导论5

14.6. SI 范例
    上面部分讨论了SI 的定义，典型的SI 问题，它们的起因和重要性。对SI 分析包括概念，建模方法学和仿真工具等的相关背景知识做了介绍。在本章，将针对一个实际例子来使用仿真工具在设计流程中来分析SI 问题。
    这是一个4 层PCB，堆栈为Signal/Power/Ground/Signal。一个DSP 芯片放置在PCB 板的中心，信号的边缘速率为500ps。在布线时，处于对串扰限制的考虑，相连线必须足够宽而不会产生过分的耦合噪声。样机制作完成以后，通过测量显示当驱动同时翻转的时候，时钟线上有比较大的耦合噪声。肉眼观察来看，时钟线网和信号线相距比较远，而且没有串扰的冲突被发现（图14-2 显示的是时钟线网的拓扑结构，信号和芯片的位置）。具体的后串扰仿真同时也显示时钟线和信号线之间的耦合是很小的。但是噪声是从哪里来的呢？
 
图14-12 PCB 上有问题的时钟网络
    由于噪声总是在驱动瞬时开关输出（SSO）时产生的，所以对电源/地噪声进行了彻底的分析。利用Sigrity 公司出品的SI 工具－SPEED97 对PCB 内部的电磁场进行了求解。图14-13 表示的是电源和地平面之间的空间电压波形图(1.51ns时刻)，14-4 表示的是波动的峰值图。从图中可以清楚的看出开关驱动源和板上去耦电容的位置。同时也注意到在图的上半部分有比较大的电源和地噪声，同时也是时钟过孔所在位置。至此，我们很清楚的知道是因为时钟的过孔耦合了电源噪声。14-15 图再一次说明了时钟过孔处的SSN 噪声。
 
图14-13 1.51ns 时电源和地之间空间噪声分布
 
图14-14. 10ns 仿真时间内电源和地平面电压峰值的空间分布图
 
图14-15 在过孔位置，时钟网络的瞬时开关噪声
    压制耦合噪声的方法十分简单。通过在时钟过孔处添加一些附加的去耦电容，该点的电源/地噪声减小，从而在时钟线上所产生的耦合噪声也降低到了噪声要求的水平。去耦电容的正确值可以通过一系列的what-if 分析来仿真得到。修改以后的PCB 经过测量验证了仿真的结果。在进行仔细的SI 分析以后我们得到了一个成功的设计。
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