原创 半导体工艺文章汇总

Architecture

Mon May 31 2010 02:18:51 GMT-0700 (Pacific Daylight Time) Design challenges in DRL

Tue Mar 02 2010 13:31:52 GMT+0800 (China Standard Time) Tabula tips time-share FPGA architecture

DFT

Mon May 31 2010 02:14:15 GMT-0700 (Pacific Daylight Time) Pattern matching: A picture is worth a thousand rules With this visual representation capability, pattern matching opens up a whole
new way to define, manage, and process design rules, and allows designers and
foundry personnel to communicate via a “language” that they both speak fluently.

Sun Feb 21 2010 15:41:13 GMT+0800 (CST) Facilitating at-speed test at the register transfer level

Tue Jan 26 2010 21:02:18 GMT-0800 (Pacific Standard Time) Design for diagnosis to improve IC yield

Sun Dec 27 2009 22:10:52 GMT-0800 (Pacific Standard Time) In-design metal fill key to physical verification turnaround
time for advanced IC designs

Sun Dec 27 2009 19:29:22 GMT-0800 (Pacific Standard Time) Bottlenecks removal in Design-For-Test flows for complex
SoCs

Timing

Sun Sep 26 2010 16:02:26 GMT+0800 (China Standard Time) How to achieve timing closure in large, complex FPGA designs

Thu Jun 24 2010 14:59:22 GMT+0800 (China Standard Time) Repeatable results with design preservation

Thu Jun 24 2010 14:55:42 GMT+0800 (China Standard Time) Time is right for clockless design

Thu Jun 24 2010 14:54:08 GMT+0800 (China Standard Time) Reducing switching power with intelligent clock gating

Thu Jun 24 2010 14:51:22 GMT+0800 (China Standard Time) Power analysis of clock gating at RTL

Mon Jun 07 2010 11:04:16 GMT+0800 (China Standard Time) Top-level MCMM closure for a multi-million-gate design

Mon May 31 2010 02:15:32 GMT-0700 (Pacific Daylight Time) Using a power grid optimizer to improve routing track utilization

Mon Apr 12 2010 17:29:09 GMT+0800 (China Standard Time) RTL synthesis can accelerate the entire implementation flow

Thu Feb 25 2010 13:23:49 GMT+0800 (China Standard Time) What if what-if analysis won't work at 28nm?

Sun Jan 17 2010 21:35:10 GMT-0800 (Pacific Standard Time) Timing Closure Methodology for Advanced FPGA Designs The Altera Timing Closure Methodology

Mon Jan 04 2010 21:42:46 GMT-0800 (Pacific Standard Time) How do you qualify netlist reduction and circuit
extraction?

Sun Dec 27 2009 19:22:45 GMT-0800 (Pacific Standard Time) Synthesizing a New Category Oasys Turns Synthesis Upside Down

Wed Nov 18 2009 18:01:04 GMT-0800 (Pacific Standard Time) Taking Exception Verifying and Generating False and Multi-cycle Path Constraints

Wed Nov 11 2009 16:41:37 GMT-0800 (Pacific Standard Time) Optimize circuit designs with better crosstalk-aware routing
techniques

Sun Nov 08 2009 23:47:53 GMT-0800 (Pacific Standard Time) Probabilistic Timing Analysis

Sun Nov 08 2009 23:47:11 GMT-0800 (Pacific Standard Time) Bridging SOC Architectures for Faster Timing Closure

Sun Nov 08 2009 23:46:27 GMT-0800 (Pacific Standard Time) Accelerate Design Closure with Multi-Core Timing Analysis and Optimization

Tue Nov 03 2009 22:11:48 GMT-0800 (Pacific Standard Time) 靜態時序分析（Static Timing Analysis）基礎及應用（下）

Tue Nov 03 2009 22:10:37 GMT-0800 (Pacific Standard Time) 靜態時序分析（Static Timing Analysis）基礎及應用（上）

Tue Nov 03 2009 22:07:42 GMT-0800 (Pacific Standard Time) Circuit Design Hint: Calculating Corner Independent Timing Closure

Thu Oct 29 2009 20:11:11 GMT+0800 Moving Data across Asynchronous Clock Boundaries

Wed Oct 28 2009 18:05:42 GMT-0700 (Pacific Daylight Time) Static Timing Analysis Increases ASIC Performance

Thu Oct 08 2009 10:36:48 GMT+0800 DIAGNOSING CDC ERRORS IN FPGAs

Thu Oct 01 2009 09:47:17 GMT+0800 Design Hint: Reduce the clock-tree power drag in your circuit implementation

Thu Oct 01 2009 07:28:51 GMT+0800 Don't Let Metastability Cause Problems in Your FPGA-Based
Design

Wed Sep 09 2009 19:23:00 GMT-0700 (Pacific Daylight Time) IP Solutions for Synchronizing Signals that Cross Clock Domains Synopsys know-how revealed!

Wed Aug 26 2009 18:31:57 GMT-0700 (Pacific Daylight Time) 成功解决FPGA设计时序问题的三大要点

Sat Aug 29 2009 21:49:11 GMT+0800 Catching Mr. X: Diagnosing CDC Errors in FPGAs

Mon Aug 10 2009 22:44:08 GMT-0700 (Pacific Daylight Time) Verification and generation of constraints

Processing

Mon Feb 01 2010 23:42:51 GMT-0800 (Pacific Standard Time) ASIC pioneer reinvents 3-D FPGAs

Mon Dec 28 2009 00:44:11 GMT-0800 (Pacific Standard Time) DRAM: the field for material and process innovation

Sun Dec 27 2009 22:17:59 GMT-0800 (Pacific Standard Time) Easier cross-domain signal protection for mixed-signal
SoCs

Mon Dec 21 2009 21:35:19 GMT-0800 (Pacific Standard Time) Making the shift from floating-gate to phase-change in non-volatile memory

Mon Oct 19 2009 20:01:29 GMT-0700 (Pacific Daylight Time) NAND Flash competition fueled by advanced lithography
technology

Fri Oct 02 2009 12:19:53 GMT+0800 Researchers present MRAM-based FPGA architecture

Mon Mar 23 2009 22:02:01 GMT-0700 (Pacific Daylight Time) Process variability becoming competitive weapon?

Sun Dec 14 2008 20:56:05 UTC+0800 How to exploit the uniqueness of FPGA silicon for security applications

Thu Dec 11 2008 13:11:02 GMT+0800 China chips: Bomb, or just a lot of firecrackers?

Sat Sep 6 2008 09:25:47 UTC+0800 A Comprehensive Approach to Manufacturing Variability

Fri Sep 5 2008 12:45:58 UTC+0800 When the Walls Get Too Thin

Fri Sep 5 2008 12:42:05 UTC+0800 Apples to Apples

Fri Sep 5 2008 12:41:37 UTC+0800 The Big eASY

Fri Sep 5 2008 12:41:12 UTC+0800 How Many Nanometers Do I Need?

Fri Sep 5 2008 12:36:03 UTC+0800 Will memristors prove irresistible?

Fri Sep 5 2008 12:35:09 UTC+0800 When atoms count

Fri Sep 5 2008 12:34:48 UTC+0800 Reading the tea leaves