原创 pwm 的veilog硬件实现

本文用介绍用verilog代码实现PWM。

其源代码如下：

module pwm(clk,write_data,cs,write_n,addr,clr_n,read_data,pwm_out);
  input[31:0] write_data;
  input clk,cs,write_n,addr,clr_n;
  output[31:0] read_data;
  output pwm_out;
 
  reg[31:0] period,pulse_width,counter,read_data;
  reg off;
  wire period_en,pulse_width_en;
//?¨ò? periodoípulse_width??′??÷μ??úèY
  always @(posedge clk or negedge clr_n)
    begin
     if(!clr_n)
       begin
         period<=32'h00000000;
         pulse_width<=32'h00000000;
       end
      else
       begin
         if(period_en)
            period<=write_data;
         else
            period<=period;
         if(pulse_width_en)
            pulse_width<=write_data;
         else
            pulse_width<=pulse_width;
        end
     end
//periodoípulse_width ??′??÷μ??á·??ê
   always @(addr or period or pulse_width)
     if(!addr)
       read_data=period;
     else
       read_data=pulse_width;
   always @(posedge clk or negedge clr_n)
      begin
        if(!clr_n)
          counter<=0;
        else
         if(counter>=period-1)
           counter<=0;
         else
           counter<=counter+1;
      end
    always @(posedge clk or negedge clr_n)
       begin
         if(!clr_n)
           off<=0;
         else
          if(counter>=pulse_width)
           off<=1;
          else
           if(counter==0)
            off<=0;
           else
            off<=off;
        end
 assign period_en=cs & !write_n & !addr;
 assign pulse_width_en=cs & !write_n & addr;
// pwmê?3?
 assign pwm_out=!off;
endmodule   

经过modelsim编译和功能仿真其功能基本正确，如下图