原创 data2mem技术

2008-7-21 09:49 2783 3 4 分类: FPGA/CPLD

i want to use Data2mem tool for my rom updating. i have rom that has size of 64kb
 with data bus of 8 bits.i used this tool for 4kb and it worked fine but some how
  for 64 kb its not working at all.
normally for this tool bmm is used. so i used and for 64kb there are 32 ramb16
 location that i have seen in place and route editor so i enter these location
  in bmm file.
here is the bmm file that i have used.
ADDRESS_SPACE i_mc8051_rom RAMB16 [0x0000:0xffff]
///////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B6 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B9 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B12 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B15 [7:0];
END_BUS_BLOCK;
///////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B64 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B67 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B70 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B73 [7:0];
END_BUS_BLOCK;


///////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B122 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B125 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B128 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B131 [7:0];
END_BUS_BLOCK;


//////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B180 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B183 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B186 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B189 [7:0];
END_BUS_BLOCK;


///////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B238 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B241 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B244 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B247 [7:0];
END_BUS_BLOCK;


///////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B296 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B299 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B302 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B305 [7:0];
END_BUS_BLOCK;


///////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B354 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B357 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B360 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B363 [7:0];
END_BUS_BLOCK;


///////////////////////////////////////////////////////////////////////////////
BUS_BLOCK
i_mc8051_rom/B412 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B415 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B418 [7:0];
END_BUS_BLOCK;


BUS_BLOCK
i_mc8051_rom/B421 [7:0];
END_BUS_BLOCK;


///////////////////////////////////////////////////////////////////////////////
END_ADDRESS_SPACE;


The thing i want to know is how to enter values on these bram location. i have
8 bit data bus.ramb16 means one location has to be 2kb.and i have 32 locations.
so how this 2kb per location will work.guide me out.i have seen xilinx data2mem
pdf file but no help in this matter.
waiting for responce.


 


next thing is i have hex file i can also use .coe format.but how to generate from hex file a coe file.


waiting for the responces.


thanks
-----------------------------------------------------------------------------
Muhammad,


 


This is how I do. Don't know if this is the right way but it works.


 


1. First, prepare .bmm file. One thing I would like to note is that use fixed primitive for coregen.


(2k x 8) Otherwise, I saw Coregen use 9-bit parity for data bit which can mess up the data2mem.


Here is my example for 32-bit ROM. (ROM.bmm)


 


//--------------------------------------------------------------------------------------------------


// myTop can be any name. I don't think PPC405 also matters.


//--------------------------------------------------------------------------------------------------


ADDRESS_MAP myTop PPC405 0


 


    ADDRESS_SPACE BOOTROM_0 RAMB32 [0x00000000:0x00003FFF]


         BUS_BLOCK


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [7:0] ;


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [15:8] ;


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [23:16] ;


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:24] ;


        END_BUS_BLOCK;


    END_ADDRESS_SPACE;


 


    ADDRESS_SPACE BOOTROM_1 RAMB32 [0x00004000:0x00007FFF]


        BUS_BLOCK


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [7:0] ;


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [15:8] ;


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [23:16] ;


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:24] ;


        END_BUS_BLOCK;


    END_ADDRESS_SPACE;


 


END_ADDRESS_MAP;


 


You need to know the exact path of block memory. I use planAhead and I think any other tool which can read .ngc or .edn should work.


 


2.  Run Map/PAR with .bmm file. Just add ROM.bmm file during ISE run. At the end of bitgen, ISE will create ROM_bd.bmm


which contains the physical location of each ROM as shown below.


 


ADDRESS_MAP myTop PPC405 0


 


 


    ADDRESS_SPACE BOOTROM_0 RAMB32 [0x00000000:0x00003FFF]


        BUS_BLOCK


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [7:0] PLACED = X4Y12;


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [15:8] PLACED = X4Y22;


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [23:16] PLACED = X4Y30;


            top/rom/rom0/u0_R1O4096X32M16P32A_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:24] PLACED = X4Y17;


        END_BUS_BLOCK;


    END_ADDRESS_SPACE;


 


 


    ///////////////////////////////////////////////////////////////////////////////


    //


    // Processor 'mb_uC' address space 'BOOTROM_1' 0x00004000:0x3300007FFF (16 KB).


    //


    ///////////////////////////////////////////////////////////////////////////////


 


    ADDRESS_SPACE BOOTROM_1 RAMB32 [0x00004000:0x00007FFF]


        BUS_BLOCK


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [7:0] PLACED = X4Y9;


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [15:8] PLACED = X4Y23;


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [23:16] PLACED = X2Y37;


            top/rom/rom1/u0_R1O4096X32M16P32B_fpga/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:24] PLACED = X4Y18;


        END_BUS_BLOCK;


    END_ADDRESS_SPACE;


 


To run data2mem, the tool should know where it can find BRAM to replace the contents.


If you didn't run with .bmm, you can manually create .bmm file using planAhead or FPGA editor for geometry.


I recommend using planAhead to read .ncd since it is much faster.


 


3. Prepare .mem file for new data. Refer data2mem manual for exact format. But basically it is just list of data with starting address.


You can jump to next address without filling every address. "0" will be inserted for any address that are not covered.


You may want to create very simple script to convert .hex to .mem (or .coe to .mem).


Let's call this file as "newROM.mem"


 


@0000


0e0000ea


18f09fe5


18f09fe5


18f09fe5


18f09fe5


18f09fe5


18f09fe5


18f09fe5


40000000


@3FFF


0f000000


 


4. Ready to run data2mem.


If your original bitstream is Top.bit, you can create new bitstream "newTop.bit"


with data2mem.


 


data2mem -bm ROM_bd.bmm -bd  newROM.bmm -bt Top.bit -o b newTop.bit


 


If you would like to verify the new data in new bitstream, dump bitstream into text file


might be useful.


 


data2mem -bm ROM_bd.bmm -bt newTop.bit > newTop.dump.txt


 


Hope this helps. I love data2mem. This is the fastest way to create new bitstream


with new ROM data without running long long ISE processes.


 


- Jay Moon


以下为我的个人小结:


1. data2mem工具认为地址空间是字节地址空间,对于做32位SOC的朋友或16位DSP的朋友需要进行4倍或2倍的处理


2. BUS_BLOCK与END_BUS_BLOCK之间的位宽要根据用户自己的实际位宽来组合


3. 注意格式,注意多个blockram初始化可以统一写在同一个.bmm里即多个ADDRESS_SPACE ...END_ADDRESS_SPACE;也可以分步法,逐步生成中间的.bit


4. 很有意思的RAM32可以用,虽然实际上我们使用的还是RAMB36(不过不用4位PARITY的)


 5. *.mem注意是使用intel格式(我们项目中用字地址),注意字地址和字节地址的关系转换,否则不正确


 


总之data2mem确实很不错很wonderful

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用户377235 2015-10-25 21:47

You really found a way to make this whole prsceos easier.
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