Tri-State Outputs
Tri-state outputs allow either a valid data signal or a high impedance signal to be driven out of an input port. The timing of either signal is important in the overall system timing of the design.
三态输出允许一个有效的数据信号或者一个高阻抗的信号，被当作一个输入端口。任意信号的时序对整个系统来说都是很重要的。
对三态输出的约束和一般的输出端口约束是一致的。
Figure 1–11 展示了一个典型的三态缓存器驱动的输出
Example 1–13 展示了对三态输出端口的约束
Example 1–13. Tri-State Output Port Constraints
# Base clock
create_clock [get_ports { clk}] \
- name { clk} \
- period 10 .0 \
- waveform {0.0 5 .0}
# Virtual clock for the output port
create_clock \
- name { clk_virt} \
- period 10 .0 \
- waveform {0.0 5 .0}
# Output constraints
set_output_delay 2. 0 \
- max \
- clock [ get_clocks {clk_virt }] \
[ get_ports {tri_out}]
set_output_delay 1. 0 \
- min \
- clock [ get_clocks {clk_virt }] \
[ get_ports {tri_out}]
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