#specify the maximum external clock delay from the external device
#指定从外部设备进来的最大外部时钟延时
set CLKAs_max 0 .200
#指定从外部设备进来的最小外部时钟延时
set CLKAs_min 0 .100
#specify the maximum external clock delay to the FPGA
#指定信号传递到FPGA的最大外部时钟延时
set CLKAd_max 0 .200
#指定信号传递到FPGA的最小外部时钟延时
set CLKAd_min 0 .100
#specify the maximum clock-to-out of the external device
#指定外部设备最大Tco延时
set tCOa_max 0 .525
#指定外部设备最小Tco延时
set tCOa_min 0 .415
#specify the maximum board delay
#定义最大的board延时（ PCB走线延时？）
set BDa_max 0 .180
#定义最小的board延时
set BDa_min 0 .120
#create the input maximum delay for the data input to the
#FPGA that accounts for all delays specified
#指定最大的输入延时（Note:即从 clkA处时钟上升沿开始计时<从 clk到
#clkA端口也有一段时延CLKAd，所以需要减去该值 >，数据进入FPGA的寄
#存器耗费的时间）
set_input_delay -clock clk \
-max [ expr $CLKAs_max + $tCOa_max + $BDa_max - $CLKAd_min] \
[get_ports {data_in}]
#create the input minimum delay for the data input to the #FPGA that
#accounts for all delays specified
#指定最小的输入延时
set_input_delay -clock clk \
-min [ expr $CLKAs_min + $tCOa_min + $BDa_min - $CLKAd_max] \
[get_ports {data_in}]
#create the input clock
#创建输入时钟
create_clock -name clkA -period 10 [get_ports clkA]
#create the associated virtual input clock
#创建与输入时钟关联的virtual clock
create_clock -name clkA_virt -period 10
#specify any uncertainty from the external clock to the virtual clock
#指定从外部时钟到virtual clock的不确定时间
set_clock_uncertainty -from { clkA_virt } -setup 0.25
#create the output clock
#创建输出时钟
create_clock -name clkB -period 5 [get_ports clkB]
#create the associated virtual input clock
#创建相关联的virtual input clock
create_clock -name clkB_virt -period 5
#specify any uncertainty from the external clock to the virtual clock
#指定从外部时钟到virtual clock的不确定时间
set_clock_uncertainty -from { clkB_virt } -setup 0.25
#determine internal clock uncertainties
#决定内部时钟不确定性
derive_clock_uncertainty
#create the input delay referencing the virtual clock
#引用vritual clock 来创建输入延时
#specify the maximum external clock delay from the external device
set CLKAs_max 0 .200
#specify the minimum external clock delay from the external
#device
set CLKAs_min 0 .100
#specify the maximum external clock delay to the FPGA
set CLKAd_max 0 .200
#specify the minimum external clock delay to the FPGA
set CLKAd_min 0 .100
#specify the maximum clock-to-out of the external device
set tCOa_max 0 .525
#specify the minimum clock-to-out of the external device
set tCOa_min 0 .415
#specify the maximum board delay
set BDa_max 0 .180
#specify the minimum board delay
set BDa_min 0 .120
#create the input maximum delay for the data input to the
#FPGA that accounts for all delays specified
set_input_delay -clock clkA_virt \
-max [ expr $CLKAs_max + $tCOa_max + $BDa_max - $CLKAd_min] \
[get_ports {data_in}]
#create the input minimum delay for the data input to the
#FPGA that accounts for all delays specified
set_input_delay -clock clkA_virt \
-min [ expr $CLKAs_min + $tCOa_min + $BDa_min - $CLKAd_max] \
[get_ports {data_in}]
#creating the output delay referencing the virtual clock
#specify the maximum external clock delay from the external
#device
set CLKBs_max 0 .100
#specify the minimum external clock delay from the external
#device
set CLKBs_min 0 .050
#specify the maximum external clock delay to the FPGA
set CLKBd_max 0 .100
#specify the minimum external clock delay to the FPGA
set CLKBd_min 0 .050
#specify the maximum clock-to-out of the external device
set tSUb_max 0 .500
#specify the hold time of the external device
set tHb 0 .400
#specify the maximum board delay
set BDb_max 0 .100
#specify the minimum board delay
set BDb_min 0 .080
#create the output maximum delay for the data output from the
#FPGA that accounts for all delays specified
set_output_delay -clock clkB_virt \
-max [ expr $CLKBs_max + $tSUb_max + $BDb_max - $CLKBd_min] \
[get_ports {data_out}]
#create the output minimum delay for the data output from the
#FPGA that accounts for all delays specified
set_output_delay -clock clkB_virt \
-min [ expr $CLKBs_min - $tHb + $BDb_min - $CLKBd_max] \
[get_ports {data_out}]
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