原创 TI DSP USB2.0仿真器（自制）

TI DSP USB2.0仿真器自制资料：

原理图

CPLD配置：

JTAG.V程序：

module JTAG(TRST,rdy,pa0,pa1,pa2,led,rdyout,JTAG_VCC,INT_8990,
   TMS_tdo,TDO_8990,TMS_8990,
   TMS_tdi,TDI_8990,JTAG_TMS,
   TMS_emu0,TMS_emu1,
   ENENT0,ENENT1,ENENT2,ENENT3,
   EN244,TOFF,
   clkin,CLK_8990,JTAG_CLK,CLKRET
   );

input rdy,JTAG_VCC,INT_8990;
output pa0,pa1,pa2,led,TRST,rdyout;

input TMS_tdo,TDO_8990,TMS_8990;
output TMS_tdi,TDI_8990,JTAG_TMS;

input TMS_emu0,TMS_emu1,ENENT3;
output ENENT0,ENENT1,ENENT2;

input clkin,CLKRET;
output CLK_8990,JTAG_CLK;

output EN244,TOFF;

//reg led;
//reg [9:0]count;

assign pa0 = INT_8990;//***
assign pa1 = 1'b1;
assign pa2 = 1'bz;//***
assign led = JTAG_TMS;
assign TRST = ENENT3;//***
assign rdyout = rdy;

assign TMS_tdi = (JTAG_VCC)?TDO_8990:1'b1;
assign TDI_8990 = TMS_tdo;
assign JTAG_TMS = (JTAG_VCC)?TMS_8990:1'b0;

assign ENENT0 = TMS_emu0;
assign ENENT1 = TMS_emu1;
assign ENENT2 = TMS_tdo;//***

assign CLK_8990 = (JTAG_VCC)?clkin:1'b0;
assign JTAG_CLK = (JTAG_VCC)?clkin:1'b0;

assign EN244 = 1'b0;
assign TOFF = JTAG_VCC;
/*
always @(posedge JTAG_TMS or negedge JTAG_VCC)
  begin
 if (!JTAG_VCC)begin count <= 10'h000;led <= 1'b0;end
 else begin
  count <= count + 1;
  if (count >= 10'h1ff)led <= 1'b0;
  else led <= 1'b1;
 end
  end
*/
endmodule

JTAGCLK.V程序：

module JTAGCLK(CLK,JCLK);
input CLK;
output JCLK;

reg counter;
reg JCLK;

always @(posedge CLK)
  begin
 counter <= counter + 1'b1;

 if (counter == 1)JCLK <= ~JCLK;
  end

endmodule

最后上传原理图和CPLD配置

https://static.assets-stash.eet-china.com/album/old-resources/2010/5/7/1ac8fd1c-adeb-4d91-9dfb-879ddb44a306.rar