module interpolate4( clk,reset,x,y
);
input clk;
input reset;
input [7:0] x;
output reg [7:0] y;
reg [1:0] cnt;
always @(posedge clk) begin
if(!reset) begin
cnt <= 0;
y <= 0;
end
else begin
cnt <= cnt +1;
if(cnt == 0)
y <= x;
else
y <=0 ;
end
end
endmodule
文章评论(0条评论)
登录后参与讨论