1,源代码
module edge_jiance(clk , ps2_clk, pos_ps2_clk,,
neg_ps2_clk, rst_n
);
input clk, ps2_clk, rst_n;
output pos_ps2_clk, neg_ps2_clk;
reg r0, r1, r2;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
r0 <= 1'b0;
r1 <= 1'b0;
r2 <= 1'b0;
end
else
begin
r0 <= ps2_clk;
r1 <= r0;
r2 <= r1;
end
assign neg_ps2_clk = r2 & (~r1) ;
assign pos_ps2_clk = (~r2) & r1;
endmodule
2.测试代码
`timescale 1 ns/ 1 ps
module edge_jiance_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg ps2_clk;
reg rst_n;
// wires
wire neg_ps2_clk;
wire pos_ps2_clk;
// assign statements (if any)
edge_jiance i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.neg_ps2_clk(neg_ps2_clk),
.pos_ps2_clk(pos_ps2_clk),
.ps2_clk(ps2_clk),
.rst_n(rst_n)
);
initial
begin
clk=0;
rst_n=0;
ps2_clk=0;
#40
rst_n=1;
end
always #10 clk = ~clk;
always #200 ps2_clk = ~ps2_clk;
endmodule
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