标签: verilog

We have been implementing every possible checks to make sure design is verified but what have we done to check our test bench ? How do we make sure that our test bench has covered everything that needs to be covered w.r.t to specification and test plans ? Here is the place “Functional Coverage” and “SVA” comes in picture!   Before we start on few guidelines to follow while working with functional coverage, I would encourage you to refer various posts on functional coverage and assertions to get high level idea on architecture and usage. Click on below links 1. http://asicwithankit.blogspot.in/2011/01/coverage-model-in-system-verilog-test.html 2. http://www.asicwithankit.blogspot.com/2012/12/system-verilog-functional-coverage.html 3. http://www.asicwithankit.blogspot.com/2013/01/the-two-door-keepers-assertion-to-make.html     Now, Basic questions can come to mind is, "what is the difference between code and functional coverage?". Let’s understand it at high level and then we will move forward to understand guidelines for functional coverage.     Sr No Code Coverage Functional Coverage    and SVA 1 Derived from design code with the help of simulation tools It is user specified, controlled approach coverage by test bench 2 Evaluate design code to check whether structure is covered or not Measures functionality part with the help of covergroup, cover point and bins (with the help of luxury feature of System Verilog  J ) (With SVA you can capture functional coverage using cover property)   To conclude with few guidelines from various posts on functional coverage and assertions: Functional coverage and code coverage both are contributing highly on sign off criteria for verification. Verification engineers have to make sure that their test plan and test environment is intelligent enough to satisfy the code/functional coverage closer. Code coverage is generated by tool with the help of the simulations generated by the test environment. So test environment should be random and intelligent enough to make sure design is covered as a part of code coverage and designer should be in agreement while code coverage review. There should be valid comments with reason for all exclusions for code coverage w.r.t to design specification. Functional coverage should be written such a way that it should be able to capture all identified functionality while defining the test plan. Coverage and assertions are very important entity in the verification process and there are few guidelines that would help in verification process. Few guidelines while working with functional coverage   Your test plan should be based on the functionality you want to verify w.r.t to specification You should have a coverage matrix with the list of cover point details w.r.t to your test plan scenario and there should be link of traceability between test scenario and cover point. Environment should have control mechanism for enabling or disabling coverage and assertions for better control ability in your environment Don’t enable functional coverage at the beginning of the verification to avoid simulation overhead in the starting phase of verification During the initial time of the verification bug ration is typically high, as you move forward to the verification bug ration would start to drop. Here is the time when you should enable coverage and analyze it Functional coverage plan needs to be updated as verification progresses As your knowledge of the design and corner case understanding increases, you should keep updating your functional coverage plan Make effective use of cover group “trigger” and sampling mechanism. (Stay tune for sampling mechanism on upcoming blog post !) Follow meaningful names of cover group and cover points. This will help when you in debug process Coverage should not be captured on failing simulations. Make sure to gathered coverage for only passing simulation. If few tests are not passing in regression first make sure to fix those issues before come to a conclusion on coverage achievement If your tests are keep exercising the same logic in design, start developing the new tests for uncovered coverage part of coverage (coverage holes) For guidelines on SVA, please refer to this article (http://www.asicwithankit.blogspot.com/2014/08/system-verilog-assertions-sva-types.html)  ! Stay tuned to understand functional coverage sampling mechanism ! Thanks, ASIC With Ankit

  Dear Readers,   Here I would like to share some understanding on keyword called  "this" . What is  "this"  in System Verilog? How does it used? Usage of  "this"  is simple but important in test bench development.   First of all lets understand What is  "this"  in System Verilog?   "this"  is a key word in System Verilog used to unambiguously refer to class properties or methods of current object. The  "this"  keyword shall only used within a non-static class methods otherwise an error shall occur.   As example is the best way to understand the most of the things, let me take a example and try to explain. Example to understand the usage of  "this"  in System Verilog:   #############################################       class  ASICwithAnkit ;          int  a ;          function new  ( int  a);             this .a = a;          endfunction  : new       endclass  : ASICwithAnkit //Class instantiation and usage ASICwithAnkit  AwA =  new  (123); $display  ("AwA.a = %d,", AwA.a); ##########################################   In above example we can see that 'a' is a member of class "ASICwithAnkit". When we initialize the memory for class for usage, we have passed a integer value '123' to its constructor (function new). The variable 'a' is local to class instance "AwA and is now 123 as we have passed this from constructor.   Hope this is useful to understand the meaning and usage of  "this"  in System Verilog.   Happy Reading ! ASIC With Ankit

Dear Readers, System Verilog has new data type called ‘queue’ which can grow and shrink. With SV queue, we can easily add and remove elements anywhere that is the reason we say it can shrink and grow as we need. Queues can be used as LIFO (Last In First Out) Buffer or FIFO (First In First Out) type of buffers. Each element in the queue is identified by an ordinal number that represents its position within the queue, with 0 representing the first element and $ represents the last element. The size of the queue is variable similar to dynamic array but queue may be empty with zero element and still its a valid data structure. Lets take a few examples to understand queue operation with different methods we have in system verilog.   ###############################################  int  a; Q = {0,1,2,3};  // Initial queue   initial begin    // Insert and delete    Q.insert (1, 1); // This means insert 1 at first element in the queue which becomes {0,1,1,2,3}    Q.delete(2); // This means delete 2 nd  element from the queue. {0,1,2,3}       //Push_front    Q.push_front (6);  //Insert ‘6’ at front of the queue. {6,0,1,2,3}       //Pop_back    a = Q.pop_back; // Poping the last element and stored it to local variable ‘a’,  a = 3 in this case. Resultant Queue = {6,0,1,2}       //push_back    Q.push_back(7) // Pushing the element ‘7’ from the back. {6,0,1,2,7}        //Pop_front:    a =Q.pop_front; Poping the first element and stored it to local variable called ‘a’, a=6 in this case. Resultant Queue = {0,1,2,7}   end #####################################################    When you create a queue System Verilog actually allocates extra space and because this we can add and remove the element based on need in our test bench. This is very useful feature in test bench implementation. System Verilog automatically allocates the additional space so we don't need to worry about the limits and queue will not run out of space.   Queue is very useful data type in System Verilog for developing a test benches. It can be used in development of various entity in the test bench like scoreboard, monitor, transaction class, drivers etc.   Hope this helps in basic understanding of queue and its methods.   Happy Reading! ASIC With Ankit

Dear Readers, We have been using standard languages and methodologies for ASIC/FPGA design and Verification activities. We as an engineer must know on history of verification activities. Today we mostly work on verification standard languages like System Verilog. The whole industry is moving to accept this language with few methodologies (RVM, VMM, AVM, OVM, UVM etc...) as their standards for new and existing product development and verification. Now since we use the industry standard languages like VHLD, Verilog, and System Verilog, we must know and understand history and importance of Verification languages. Let’s understand how we reached to a System Verilog usage? What are the other different verification languages engineers were using in past few decades? How did they start their usage from Verilog to System Verilog for verification? Let’s go back to history and understand these questions. When Verilog first developed in mid-80, main requirement and usage of this language was to develop synthesizable RTL with not much complexity. Revolution started by late 1980s. By late 80s synthesis and simulation triggered a revolution for EDA industry. As time passed, In 90s industry realized a tremendous need to solve complex verification problems due to complex designs. This was the time when EDA Company played a key role in filling the requirement to solve this verification issues. Those days verification languages which become popular and people started using those were proprietary to some companies! Best examples are ‘Open Vera’ and ‘e’ language. Since these languages were proprietary to EDA companies, some people were using the Object Oriented Languages like C++. During those days some users were using Verilog to develop their testbench, looks interesting, Isn’t it! The problems gets started during 1990s when Verilog become an industry standard. In 1980s a company called Gateway Design Automation developed a logic simulator called Verilog-XL and Cadence acquired in 1989 with right. Now with a new strategy Cadence put the language in to the public domain with the intention that Verilog should become a standard. After this Verilog HDL is now maintained by Accellera a nonprofit making organization. In 1995 Verilog HDL became IEEE standard. Accellera came up with revised versions in 2001 and then in 2005 and industry taking this as standard and moved ahead. Accellera have also developed a new standard called ‘System Verilog’ which extends Verilog with newly added many feature with the concept of Object Oriented Programing. System Verilog then became an IEEE standard (1800-2005) in 2005. System Verilog is a super set of Verilog plus all the features known to be necessary for traditional verification. System Verilog is being used mostly in Verification activities because of higher level abstraction and user friendly features. Today System Verilog is already became a standard for Verification activities and most of the companies have started accepting his beauty! In addition to System Verilog usage and acceptance people have come up with few methodologies like (RVM, VMM, AVM, OVM, UVM etc…) With the addition of this type of methodologies Verification environments are becoming easy to handle, user friendly and most importantly the environments are becoming re-usable! Happy Reading! Ankit Gopani

之前因为项目中FPGA开发的需要，学习了夏宇闻教授的《Verilog数字系统设计教程》，大约在2011年底初略学习完第一遍，到现在已经一年多了。温故而知新，于我来说不一定知新，但温故肯定会更牢固。   首先，给大家说说什么是FPGA,什么是Verilog.   FPGA（现场可编程门阵列）就是可灵活的、几乎可全配置的数字芯片，能实现定制的数字体系功能。   而Verilog是是一种硬件描述语言(HDL). 通过Verilog语言和综合工具，人们可以从底层的门级电路设计彻底解放出来，目前解放到了寄存器级，以后肯定会实现在更高级的解放。   Verilog是目前最流行的数字体系设计语言。形象的比喻：Verilog相当于一门“外语”，而FPGA编译器是能听懂Verilog这门外语的“老外农民”，FPGA相当于一块有限资源，有限面积的“试验田地”。这个“老外农民”在FPGA这个田地里，能把Verilog的描述生成相应的农作物--“电路”，并能开花结果，收成可观。   1、以绪论为引，整书主体分为4部分 ：Verilog数字设计基础、设计和验证部分、设计示范和实验练习题、语法篇。一本书的结构是否齐全，是否条理清晰，结构是否有机关联，是否经典实用，作者的水平及用心，往往从目录就能看出许多。夏老师的这本书的确是学习Verilog的经典教材。看目录建议从大处着手，对整个书的全局有一个初步印象。书中每一章最后都有小结，小结都是每一章的精华知识点。   2、整书的回顾。 第一部分主要是Verilog常用到的语法及结构。Verilog的特点是风格与C相似，学过C的人很快能上手。不同是：C语言是顺序执行，更加抽象，花样很多，这是因为C语言后面有一个强大的操作系统和运行环境。Verilog则不同，可以把Verilog的程序内容分为两部分：一部分是于运行软件和环境相关，如“系统任务和编译预处理”这部分对硬件出身的初学者比较复杂，可以于C接口，往往不可综合；另一部分是所要的设计对象，通过综合后有实际硬件相对应的可综合部分，这部分主要是组合逻辑和时序逻辑以及各模块及其形成的顶层结构，这部分 与硬件直接相关，是对硬件实体的描叙。   第1章：《Verilog的基本知识》，讲述了Verilog HDL的历史，与VHDL的比较，其设计的优点，设计流程。Verilog因为形成了标准化而兼容各个厂商，使用上能够与工艺具体参数等无关，加上广泛的C语言基础人群(泛C联盟)，所以Verilog在数字设计中比重越来越重。System Verilog的出现更是集成了设计、验证等诸多功能，更适合于可重用的IP设计及验证。具体的知识点是要理解Top_Down的设计概念。在顶层设计中，自己的体会是有两层：1、整个顶层的行为及功能需求。2、对应的顶层硬件架构和子模块来支撑这个功能需求。Top-Down的系统难点在于Top层的规划，Down的难点在于细节的把握和算法的实现。Top层的规划，特别是大型的数字系统设计，这需要系统设计方法论的熟悉和有关系统的知识。其中一个典型的系统设计方法论的例子是：控制，输入，输出要分开来进行划分。应用系统方法的设计在扩展升级性，问题定位及维护性，设计重用性等方面上会有更好的性能。 实际设计中，自己体会到的细节工具有：流程图设计、电路结构图设计、波形时序图设计。   第2章：《Verilog语法的基本概念》，将实际电路抽象影射为5个级别2类型：行为描述类型：(1)系统级、(2)算法级、(3)RTL级；结构描述类型：(4)门级 (5)开关级。描述了模块的基本结构。基本概念如：并行性，层次结构性，可综合性及测试模块。   第3章：《模块的结构、数据类型、变量和基本运算符号》，模块分为端口I/O说明，内部信号声明和逻辑功能定义。逻辑产生的三种方式：用连续赋值assign语句、用实例元件、用always块。三种方式产生的所有逻辑均通过变量名来进行相互连接。共有19种数据类型： reg, wire, integer, parameter ; large, medium, scalared,time,small,tri,tio,tirl,triand,trior,trireg,vectored,wand,wor，memory型。最常用的是前面4种。后面15种大多与基本逻辑单元建库相关。而所有数据又可以分为常量（主要为数字和parameter）和变量（wire,reg,memory型等）。Assign或门驱动的变量主要wire型。而always模块内赋值的必须定义为reg型。Memory型用于存储器建模，如reg mema 。运算符的含义及优先顺序，运算符分算术运算、位运算、逻辑/关系运算等等。运算符分单目，双目，三目运算符。注意“=”是否是“非阻赛赋值”还是“小于等于”是取决于所在语句的位置，所以应用上不会混乱。   第4章：《运算符、赋值语句和结构说明语句》，学习的要点是赋值语句和块语句。   第5章：《条件语句、循环语句、块语句与生成语句》，这章是设计应用中最重要的语法。if_else语句，这种语句综合出来为条件判断控制的多路器Mux. else总是和上面最近的if配对。当只有if无else时，组合逻辑会综合成锁存器。Case语句是多分支选择语句，类似于C语言中的switch(表达式)-case常量N:语句N;语法上更简洁,为case(表达式)-常量N:语句N; default: 语句; endcase。不同的是Verilog中是硬件跳转。case相当于If_else语句的并行扩展。不同的是else-if是1bit控制位，2选1的选择器；而case是多bit位，多选择的多路器。同样，组合逻辑中case缺乏default项容易生成锁存器。Verilog中的循环语句有四种：forever，repeat, while, for语句。因为自己对其生成对应的硬件结构不甚清楚，往往在可综合语言中，循环语句用得很少，一般都用if-else语句来代替。顺序块begin-end和并行块fork-join、生成块generate-endgenerate。   第6章：《结构语句、系统任务、函数语句和显示系统任务》。有4种结构说明语句：initial,always,task,function.其中可综合设计中always是最常用，task及function通过封装功能和调用，能够增强程序的可读性和提高编程效率，initial在testbench中能实现初始化。注意关键词“or”“，”只能用于always@()中，而条件逻辑判断需要用”||”，有一次弄混了，编译不通过。系统任务主要用于测试模块及验证。   第7章：《调试用系统任务和常用编译预处理语句》。主要用于测试模块的编写。其中感觉用的比较多的有$random,`define,`timescale,$readmemb,`include等。   第8章：《语法概念总复习练习》。有28道练习题。   第9章：《Verilog HDL模型的不同抽象级别》，叙述了门级结构描述，行为描述建模。   第10章：《如何编写和验证简单的纯组合逻辑模块》，讲述了加法器、乘法器，比较器、多路器等的设计。介绍了总线操作和流水线。   第11章：《复杂数字系统的构成》，初步介绍数字系统的概念，如组合逻辑，时序逻辑，数据保存及流动，同步时序体系。要点在于理解同步时序逻辑的意义。同步方法有:1,建立同步机制，如采用RAM和FIFO缓存.2,同步码或同步信号线。3、异步时钟域间数据传输需要注意同步。   第12章：《同步状态机的原理、结构和设计》，这一章开始讲述状态机。简单模块往往两段或一段写完；复杂模块推荐状态机的三段式写法：“初始状态和current_state=next_state”模块，“输入及状态转移”模块，“状态及输入控制输出”模块。独热码的使用。例12.4应该好好学习，三段式的好处在于解耦了各个要素，便于查错，优化与修改。也就是：第一部分说明初始状态，current_state=next_state，第二部分是状态机的状态转化的描述，第三部分是每一步状态的组合逻辑的描述。这样写调理更加清晰，也更加利于综合器综合。   第13章：《设计可综合的状态机的指导原则》，描述能更好地可综合的实际设计要求：状态机应该由唯一时钟触发；不要使用综合工具来设计异步状态机。Always块中应该避免组合反馈回路，曾经设计遇到综合后告警combinational loop问题，就是形成了组合反馈回路。状态机的置位和复位。   第14章：《深入理解阻塞和非阻塞赋值的不同》，在可综合中，非阻塞赋值事实上是寄存器在时钟跳变沿赋值，但它本身的原值未变，可以作为其他寄存器的输入。就是寄存器的值从时钟沿到来到其值的改变需要一定的时间，而时钟沿的沿及skew肯定需要少于这个时间。而阻塞赋值是我们通常意义上的赋值，这个值变化之后，后面的句子引用它得到的也是变化后的值。往往时序逻辑采用非阻塞赋值，而组合逻辑采用阻塞赋值。   第15章：《较复杂时序逻辑电路设计实践》，开始讲叙实际设计例子。如序列检测，I2C总线接口设计，I2C例子学习对工作中深入理解I2C总线的工作原理很有帮助。   第16章：《复杂时序逻辑电路设计实践 》，是15章的继续深入和扩展。继续深入I2C总线的Verilog设计，介绍了EEprom 读写所用的I2C接口的Verilog程序。讲解了EEprom的行为模型，EEprom_WR读写器的可综合Verilog模型，内部读写总线的信号源模块，最终用顶层将这三者连接起来，形成一个可仿真的小系统。真正需要的部分为EEprom_WR读写器的可综合Verilog模型，但为了得到正确的读写器的可综合模型，需要一个环境来验证这个模型的正确性，所以有信号源和EEprom的行为模型。认真学习能有很多收获，自己在这章中收获不少，使用设计技巧自觉有两点：1、采用FF来进行标志一段程序（如任务）的完成与否。2、可以判断自己，之后的语句中又可以改变掉自己。这在后续在项目中设计SPI接口程序时得以应用。   第17章：《简化的RISC_CPU设计》，这一章更为系统，使得原来很神秘的CPU清晰地展示它的原理和基本组成，涉及的知识有计算机结构和相关体系控制。当然实际的CPU或者软核，比这个要复杂的多，但基本原理相通。系统学是一门很深的学问，涉及系统的划分和配合。划分相当于复杂问题的解耦，而配合需要可靠稳定的接口。这都需要很深的理解。一句话：系统需要模块化设计，而模块化需要稳定可靠的标准化的接口。   第18章：《虚拟仪器/接口、IP和基于平台的设计方法及其在大型数字系统设计中的应用》，介绍了复杂系统设计的手段和工具：软/硬IP核,宏单元，虚拟仪器和接口。IP分为设计IP和验证IP. 介绍了虚拟接口联盟(VSIA)的组织。主要的IP供应商。   第三部分是《设计示范与实验练习》，像练习12，利用SRAM设计一个FIFO,有一年华为海思招聘数电的一道笔试题就是考FIFO的设计，这个在对外部高速接口的同步设计中几乎是必须的。第四部分是语法篇，讲述了Verilog HDL IEEE 1364标准，Verilog语言的参考手册。其中在408页有一个有趣的算法相关的例子 Pythagoras(x,y,z)。计算平方和的开方根，采用了迭代的计算方法，让我看了好半天才看懂其原理，但这个应该是不能综合的模块没，迭代的方法是不是属于数值计算？可惜没有正式学过这方面系统的知识。   本文的最后强烈推荐一下夏教授夏老师主持的论坛：http://bbs.eeworld.com.cn/thread-222470-1-1.html，有志于学习Verilog和FPGA的同学可以上去浏览和咨询问题。夏教授是中国推广Verilog的第一人。也是一个很热心和乐于助人和做实事的老教授，现已退休，一直在为强大中国的数字系统设计事业做出无私、持续、开创性的贡献。希望大家一起来支持发展这个事业。我当初是因为项目开发的需求，买了夏老师的教材，学习了他的书的过程中，又因为一些不懂的问题，斗胆发邮件请教老师，没想到老师能抽出宝贵的时间给我作答和解惑，因为那时还不知道他的论坛（如果有技术问题，希望大家去论坛问而不是邮件，这样可以节约老师的时间，统一作答；同时论坛里有许多案例可供学习），这样我也算是老师的弟子。后来又知道夏老师在“北京至芯科技”做培训事业，有志于此而有条件的，强烈推荐可以去参加老师的培训（约三个月），当当夏老师的 最后几批关门弟子。