原创 nand flash控制器

s3c2440内部集成有内部sram（steppingstone），当选择从nand flash启动的时候，nand flash的前4k代码将会自动copy到内部sram中后运行。
（一）nand flash控制器的特性：
1、支持读/写/编程 NAND FLASH内存
2、系统复位后nand flash的前4k代码自动copy到内部sram，copy完  成后从sram启动，此时内部sram被映射为nGCS0。（当OM[1：0]=    00时使能NAND FLASH 启动模式）
3、支持硬件ECC校验
4、系统启动后内部sram可以用做其他的用途。
（二）操作nand flash方法
1、设置nand flash配置寄存器NFCONF
2、向命令寄存器NFCMD写入操作命令
3、向地址寄存器NFADDR写入地址
4、读/写数据前要读取状态寄存器NFSTAT来判断nand flash是否处于   忙状态。
（三）ECC
nand flash的页为512B。在读写的时候每页会产生3个B大小的ECC校验码。
   24bot ECC校验码=18bit 线校验码+8位列校验码
（四）NAND FLASH特殊功能寄存器的详细说明

1、配置寄存器NFCONF（地址：0x4e000000）    0x0000 0100 

    位                功能                                         初始值

   [15：14]    保留    
   [13：12] TACLS:  CLE和ALE持续时间设置（0-3）          01 
            持续时间=HCLK*TACLS

   [11]      保留

   [10：8]  TWPRH0:   TWPRH0持续时间设置（0-7）          000 
            持续时间=HCLK*(设定值TWPRH0+1)
   [7]      保留
   [6：4]   TWRPH1 持续时间设置（0-7）                              000
           

        Advance NAND flash memory for auto-booting
         0: Support 256 or 512 byte/page NAND flash memory
         1: Support 1024 or 2048 byte/page NAND flash memory
         This bit is determined by NCON0 pin status during reset
         and wake-up from sleep mode.

   [2]   PageSize  Nandflash 页设定（只读）                   (HW set)GPG13

        NAND flash memory page size for auto-booting AdvFlash
         PageSize
         When AdvFlash is 0,0: 256 Word/page, 1: 512 Bytes/page
         When AdvFlash is 1,0: 1024 Word/page, 1: 2048 Bytes/page
         This bit is determined by GPG13 pin status during reset
         and wake-up from sleep mode. After reset, the GPG13 can
         be used as general I/O port or External interrupt.

  [1]  AddrCycle (Read only)    地址周期设定            （HW set）GPG14

        NAND flash memory Address cycle for auto-booting
      AdvFlash AddrCycle
      When AdvFlash is 0,
               0: 3 address cycle 1: 4 address cycle
      When AdvFlash is 1,
              0: 4 address cycle 1: 5 address cycle
     This bit is determined by GPG14pin status during reset
       and wake-up from sleep mode. After reset, the GPG14can
     be used as general I/O port or External interrupt.

[0] BusWidth (R/W) 总线宽度设定                          H/W Set(GPG15)

       NAND Flash Memory I/O bus width for auto-booting and
   general access.
        0: 8-bit bus 1: 16-bit bus
        This bit is determined by GPG15 pin status during reset
   and wake-up from sleep mode.
        After reset, the GPG15 can be used as general I/O port or
    External interrupt.
        This bit can be changed by software.

2、控制寄存器NFCONT（地址：0x4e000004）                 0x0384

 [15:14]    保留

 [13] Lock-tight                                                                          0

     Lock-tight configuration
       0: Disable lock-tight 1: Enable lock-tight,

        Once this bit is set to 1, you cannot clear. Only reset or
    wake up from sleep mode can make this bit disable(can
    not cleared by software).

 [12] Soft Lock configuration                                                  1
             0: Disable lock 1: Enable lock

 [11] 保留

 [10]EnbIllegalAccINT                                             0

   Illegal access interrupt control
     0: Disable interrupt 1: Enable interrupt
    Illegal access interrupt is occurred when CPU tries to
     program or erase locking area (the area setting in
     NFSBLK(0x4E000038) to NFEBLK(0x4E00003C)-1).

 [9]EnbRnBINT                                                  0

    RnB status input signal transition interrupt control
               0: Disable RnB interrupt         1: Enable RnB interrupt 

 [8] RnB_TransMode                                              0

      RnB transition detection configuration
           0: Detect rising edge             1: Detect falling edge

 [7] 保留 

 [6] SpareECCLock                                                   1

          Lock spare area ECC generation.
           0: Unlock spare ECC                  1: Lock spare ECC
          Spare area ECC status register is FSECC(0x4E000034)

[5]MainECCLock                                                        1

         Lock Main data area ECC generation
              0: Unlock main data area ECC generation
              1: Lock main data area ECC generation
          Main area ECC status register is NFMECC0/1(0x4E00002C/30)

[4]InitECC                                                                 0

       Initialize ECC decoder/encoder(Write-only)
          1: Initialize ECC decoder/encoder

[3：2]保留                                                                   00

[1]Reg_nCE                                                                   1

         NAND Flash Memory nFCE signal control
            0: Force nFCE to low (Enable chip select)
            1: Force nFCE to high (Disable chip select)
         Note: During boot time, it is controlled automatically.
              This value is only valid while MODE bit is 1

[0]MODE                                                                         1

          NAND flash controller operating mode
            0: NAND flash controller disable (Don’t work)
            1: NAND flash controller enable

3、命令寄存器NFCMMD（地址：0x4e000008）

   [15:8]    保留
   [7：0]    命令寄存器                        0x00

4、地址寄存器NFADDR（地址：0x4e00000C）

 5、数据寄存器NFDATA（地址：0x4e000010）

以上转自http://bestlihj.blog.163.com/blog/static/5719330520081127102216614/

读NAND Flash的步骤

1、设置NFCONF、NFCONT

NFCONF 要根据NAND 的时间特性，进行计算。

NFCONT使能NAND Flash控制器、禁止控制引脚信号nFCE、初始化ECC等。

2、通常要复位NAND Flash

3、发出读命令

4、发出地址信号

5、循环检查NFSTAT位0，NAND Flash状态寄存器

6、连续读NFDATA寄存器512次，得到一页数据（512字节）

循环执行3、4、5、6这4步，直到读出所有数据

7、最后禁止NAND Flash

步骤参考《完全手册》，韦山东

附件包含《完全手册》中读NAND Flash 的操作实例

其中leds.c是根据YL-PS3C2440所写，其中未启动MMU所以和MMU的leds.c有所不同，并因此修改了下Makefile和nand.ldshttps://static.assets-stash.eet-china.com/album/old-resources/2009/2/7/8bc93642-a3a5-4d3f-9602-9b4630704e46.rar