原创 VLSI Interview question 2

• 1) Chip utilization depends on ___.

• 2) In Soft blockages ____ cells are placed.

• 3) Why we have to remove scan chains before placement?

• 4) Delay between shortest path and longest path in the clock is called ____.

• 5) Cross talk can be avoided by ___.

• 6) Prerouting means routing of _____.

• 7) Which of the following metal layer has Maximum resistance?

• 8) What is the goal of CTS?

• 9) Usually Hold is fixed ___.

• 10) To achieve better timing ____ cells are placed in the critical path.

• 11) Leakage power is inversely proportional to ___.

• 12) Filler cells are added ___.

• 13) Search and Repair is used for ___.

• 14) Maximum current density of a metal is available in ___.

• 15) More IR drop is due to ___.

• 16) The minimum height and width a cell can occupy in the design is called as ___.

• 17) CRPR stands for ___.

• 18) In OCV timing check, for setup time, ___.

• 19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.

• 20) The Solution for Antenna effect is ___.

• 21) To avoid cross talk, the shielded net is usually connected to ___.

• 22) If the data is faster than the clock in Reg to Reg path ___ violation may come.

• 23) Hold violations are preferred to fix ___.

• 24) Which of the following is not present in SDC ___?

• 25) Timing sanity check means (with respect to PD)___.

• 26) Which of the following is having highest priority at final stage (post routed) of the design ___?

• 27) Which of the following is best suited for CTS?

• 28) Max voltage drop will be there at(with out macros) ___.

• 29) Which of the following is preferred while placing macros ___?

• 30) Routing congestion can be avoided by ___.

• 31) Pitch of the wire is ___.

• 32) In Physical Design following step is not there ___.

• 33) In technology file if 7 metals are there then which metals you will use for power?

• 34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

• 35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

• 36) Difference between Clock buff/inverters and normal buff/inverters is __.

• 37) Which configuration is more preferred during floorplaning ?

• 38) What is the effect of high drive strength buffer when added in long net ?

• 39) Delay of a cell depends on which factors ?

• 40) After the final routing the violations in the design ___.

• 41) Utilisation of the chip after placement optimisation will be ___.

• 42) What is routing congestion in the design?

• 43) What are preroutes in your design?

• 44) Clock tree doesn't contain following cell ___.

• Answers:

• Below are the sequence of questions asked for a physical design engineer.

• Answer to this question depends on your interest, expertise and to the requirement for which you have been interviewed.

• Well..the candidate gave answer: Low power design

• Refer here and browse for different low power techniques.

• Leakage
  current of a gate is dependant on its inputs also. Hence find the set
  of inputs which gives least leakage. By applyig this minimum leakage
  vector to a circuit it is possible to decrease the leakage current of
  the circuit when it is in the standby mode. This method is known as
  input vector controlled method of leakage reduction.

• -Reduce switching activity by designing good RTL
• -Clock gating
• -Architectural improvements
• -Reduce supply voltage
• -Use multiple voltage domains-Multi vdd

• Voltage and Current

• Refer here for power planning.

• -Spread macros
• -Spread standard cells
• -Increase strap width
• -Increase number of straps
• -Use proper blockage

• -Spread macros
• -Spread standard cells
• -Use proper blockage

• (buffers
  are inserted for fixing fanout voilations and hence they reduce setup
  voilation; otherwise we try to fix setup voilation with the sizing of
  cells; now just assume that you must insert buffer !)

• Near to capture path.

• Because
  there may be other paths passing through or originating from the flop
  nearer to lauch flop. Hence buffer insertion may affect other paths
  also. It may improve all those paths or degarde. If all those paths
  have voilation then you may insert buffer nearer to launch flop
  provided it improves slack.

• Refer here for floor planning.

• -It may be power planning- because you found more IR drop
• -It may be low power target-because you had more dynamic and leakage power
• -It may be macro placement-because it had more connection with standard cells or macros
• -It may be CTS-because you needed to handle multiple clocks and clock domain crossings
• -It may be timing-because sizing cells in ECO flow is not meeting timing
• -It may be library preparation-because you found some inconsistancy in libraries.
• -It may be DRC-because you faced thousands of voilations

• -Single clock-normal synthesis and optimization
• -Multiple clocks-Synthesis each clock seperately
• -Multiple clocks with domain crossing-Synthesis each clock seperately and balance the skew

• -It is specific to your project
• -More the clocks more challenging !

• -Multiple clocks-->synthesize seperately-->balance the skew-->optimize the clock tree

• -If
  it is from seperate clock sources (i.e.asynchronous; from different
  pads or pins) then balancing skew between these clock sources becomes
  challenging.

• -If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy.

• To balance skew (i.e. flop to flop delay)

• Switching
  of the signal in one net can interfere neigbouring net due to cross
  coupling capacitance.This affect is known as cros talk. Cross talk may
  lead setup or hold voilation.

• -Double spacing=>more spacing=>less capacitance=>less cross talk
• -Multiple vias=>less resistance=>less RC delay
• -Shielding=> constant cross coupling capacitance =>known value of crosstalk
• -Buffer insertion=>boost the victim strength

• -High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to either VDD or VSS.

• Coupling capacitance remains constant with VDD or VSS.

• width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less cross talk

• Why
  clock?-- because it is the one signal which chages it state regularly
  and more compared to any other signal. If any other signal switches
  fast then also we can use double space.

• Double spacing=>width is more=>capacitance is less=>less cross talk

• Multiple vias=>resistance in parellel=>less resistance=>less RC delay

• Buffer
  increase victims signal strength; buffers break the net
  length=>victims are more tolerant to coupled signal from aggressor.

• I am getting several emails
  requesting answers to the questions posted in this blog. But it is very
  difficult to provide detailed answer to all questions in my available
  spare time. Hence i decided to give "short and sweet" one line answers
  to the questions so that readers can immediately benefited. Detailed
  answers will be posted in later stage.I have given answers to some of
  the physical design questions here. Enjoy !
  

• Chip design has I/O pads; block design has pins.

• Chip design uses all metal layes available; block design may not use all metal layers.

• Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.

• Chip design requires several packaging; block design ends in a macro.

• First check flylines i.e. check net connections from macro to macro and macro to standard cells.

• If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.

• If input pin is connected to macro better to place nearer to that pin or pad.

• If macro has more connection to standard cells spread the macros inside core.

• Avoid criscross placement of macros.

• Use soft or hard blockages to guide placement engine.

• Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.

• Hierarchical design takes more run time; Flattened design takes less run time.

• 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

• Herculis from Synopsys, Caliber from Mentor Graphics.

• Netlist, Technology library, Constraints, SPEF or SDF file.

• Provide soft or hard blockage

• By checking the total area of the design you can decide die size.

• Poly

• 
  Because top two metal layers are required for global routing in chip
  design. If top metal layers are also used in block level it will create
  routing blockage.

• Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!

• Metal layers: See your tech file. generally for 90nm it is 7 to 9.

• Technology: Again look into tech files.

• Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc

• Clocks: Look into your design and SDC file !

• You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

• Depends on your design.

• For synthesis: RTL, Technology library, Standard cell library, Constraints

• For Physical design: Netlist, Technology library, Constraints, Standard cell library

• Clock definitions

• Timing exception-multicycle path, false path

• Input and Output delays

• 
  Get the total core power consumption; get the metal layer current
  density value from the tech file; Divide total power by number sides of
  the chip; Divide the obtained value from the current density to get
  core power ring width. Then calculate number of straps using some more
  equations. Will be explained in detail later.

• Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

• Prelayout: Setup, Max transition, max capacitance

• Post layout: Hold

• Setup: upsize the cells

• Hold: insert buffers

• Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

• Output pin.

• Increase power metal layer width.

• Go for higher metal layer.

• Spread macros or standard cells.

• Provide more straps.

• 
  Increased net length can accumulate more charges while manufacturing of
  the device due to ionisation process. If this net is connected to gate
  of the MOSFET it can damage dielectric property of the gate and gate
  may conduct causing damage to the MOSFET. This is antenna problem.

• Decrease the length of the net by providing more vias and layer jumping.

• Insert antenna diode.

• P increase->dealy increase

• P decrease->delay decrease

• V increase->delay decrease

• V decrease->delay increase

• T increase->delay increase

• T decrease->delay decrease

• Click here to see the flow diagram

• Gate delay

• Transistors
  within a gate take a finite time to switch. This means that a change on
  the input of a gate takes a finite time to cause a change on the
  output.[Magma]

• Gate delay =function of(i/p transition time, Cnet+Cpin).

• Cell delay is also same as Gate delay.

• Cell delay

• For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

• Intrinsic delay

• Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

• It
  is defined as the delay between an input and output pair of a cell,
  when a near zero slew is applied to the input pin and the output does
  not see any load condition.It is predominantly caused by the internal
  capacitance associated with its transistor.

• This
  delay is largely independent of the size of the transistors forming the
  gate because increasing size of transistors increase internal
  capacitors.

• Net Delay (or wire delay)

• The
  difference between the time a signal is first applied to the net and
  the time it reaches other devices connected to that net.

• It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

• Wire delay =fn(Rnet , Cnet+Cpin)

• Linear Delay Model (LDM)

• Non Linear Delay Model (NLDM)

• Wire load model is NLDM which has estimated R and C of the net.

• Because it has less resistance and hence leads to less IR drop.

• Upsizing

• Downsizing

• Buffer insertion

• Buffer relocation

• Dummy buffer placement

• negative slack==> there is setup voilation==> deisgn can fail

• IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.

• If Idrop is more==>delay increases.

• crosstalk==>there can be setup as well as hold voilation.

• There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.

• If IR drop is more==>delay increases.

• 
  Due to high current flow in the metal atoms of the metal can displaced
  from its origial place. When it happens in larger amount the metal can
  open or bulging of metal layer can happen. This effect is known as
  Electro Migration.

• Affects: Either short or open of the signal line or power line.

• Global Routing

• Track Assignment

• Detail Routing

• Source Latency

• It
  is known as source latency also. It is defined as "the delay from the
  clock origin point to the clock definition point in the design".

• Delay from clock source to beginning of clock tree (i.e. clock definition point).

• The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

• Network latency

• It
  is also known as Insertion delay or Network latency. It is defined as
  "the delay from the clock definition point to the clock pin of the
  register".

• The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

• Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

• If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

• Routing

• Distribution of clock from the clock source to the sync pin of the registers.

• H tree, Balanced tree, X tree, Clustering tree, Fish bone

• Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.

• Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.

• What is the difference between hard macro, firm macro and soft macro?

• What are IPs?

• Hard
  macro, firm macro and soft macro are all known as IP (Intellectual
  property). They are optimized for power, area and performance. They can
  be purchased and used in your ASIC or FPGA design implementation flow.
  Soft macro is flexible for all type of ASIC implementation. Hard macro
  can be used in pure ASIC design flow, not in FPGA flow. Before bying
  any IP it is very important to evaluate its advantages and
  disadvantages over each other, hardware compatibility such as I/O
  standards with your design blocks, reusability for other designs.

• Soft macros are in synthesizable RTL.

• Soft macros are more flexible than firm or hard macros.

• Soft macros are not specific to any manufacturing process.

• Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area, or power.

• Soft
  macros carry greater IP protection risks because RTL source code is
  more portable and therefore, less easily protected than either a
  netlist or physical layout data.

• From the
  physical design perspective, soft macro is any cell that has been
  placed and routed in a placement and routing tool such as Astro. (This
  is the definition given in Astro Rail user manual !)

• Soft macros are editable and can contain standard cells, hard macros, or other soft macros.

• Firm macros are in netlist format.

• Firm macros are optimized for performance/area/power using a specific fabrication technology.

• Firm macros are more flexible and portable than hard macros.

• Firm macros are predictive of performance and area than soft macros.

• Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPs !).

• Hard macos are targeted for specific IC manufacturing technology.

• Hard macros are block level designs which are silicon tested and proved.

• Hard macros have been optimized for power or area or timing.

• In physical design you can only access pins of hard macros unlike soft macros which allows us to manipulate in different way.

• You have freedom to move, rotate, flip but you can't touch anything inside hard macros.

• Very
  common example of hard macro is memory. It can be any design which
  carries dedicated single functionality (in general).. for example it
  can be a MP4 decoder.

• Be aware of features and
  characteristics of hard macro before you use it in your design... other
  than power, timing and area you also should know pin properties like
  sync pin, I/O standards etc

• LEF, GDS2 file format allows easy usage of macros in different tools.

• Hard
  macro is a block that is generated in a methodology other than place
  and route (i.e. using full custom design methodology) and is brought
  into the physical design database (eg. Milkyway in Synopsys; Volcano in
  Magma) as a GDS2 file.

• Here is one article published in embedded magazine about IPs. Click here to read.

• "Hard Macro Placement in Complex SoC Design" - view and read article from soccentral

• "Hard Macro Placement in Complex SoC Design" - download white paper

• "Local Search for Final Placement in VLSI Design" - download

• "Consistent Placement of Macro-Blocks Using Floorplanning and standard cell placement" - download

• "A Timing-Driven Soft-Macro Placement And Resynthesis Method In Interaction with Chip Floorplanning" - download

Answer:

Clock net is one of the High Fanout Net(HFN)s. The clock buffers are
designed with some special property like high drive strength and less
delay. Clock buffers have equal rise and fall time. This prevents duty
cycle of clock signal from changing when it passes through a chain of
clock buffers.

Normal buffers are designed with W/L ratio such that sum of rise time
and fall time is minimum. They too are designed for higher drive
strength.