原创 ASIC Test Methodology Simulation Engineer

Questions

1. What will happen when there is hold time violation in one of the flipflops in a scan chain?

2. How do detect which FlipFlop has the violation?

3. How many states a JTAG TAP Controller has?

4. Draw the transistor level diagram of a Tri-state buffer?

5. How to get controllability and observability on a combinational input which feeds to tri-state buffer?

6. Difference between static and local variable in C?

7. Draw the timing diagram of a scan flip flop indicating shift and capture mode?

8. Draw a low pass filter and derive its transfer characteristics?

9. Write down all conditional looping and unconditional looping statements in the programming languages that you know?

10. What is transition fault? How to detect it?

11. What is IDDQ testing? What are the problems with technology scaling on IDDQ testing?

12. Design a circuit for frequency divider/3 with 50% duty cycle?

13. Draw LFSR, MISR register and tell its uses?

14. How to avoid deadlocks in pipelined design?

15. Difference between structural and functional testing?

16. What is fault model? Tell some fault models?

17. Describe MBIST checker board algorithm?

18. Explain D-algorithm (combinational test vector generator)?