原创 Encounter_Command_Script: Power Planning_电源_地规划

 2009-8-20 10:32  5367 6 6 分类: 工程师职场

#Encounter_Command_Script: Power Planning
#Calculate Power and Ground Stripe, Ring width
#电源/地 Ring Stripe宽度计算
#Reference Perl
#usage:
#parameter:

Reference:
https://ccnet.stanford.edu/cgi-bin/course.cgi?cc=ee371&action=handout_download&handout_id=ID12433530198237

Reference Calculation:
here are two types of power planning and management. They are core cell power management and I/O cell power management. In former one VDD and VSS power rings are formed around the core and macro.
In addition to this straps and trunks are created for macros as per the
power requirement. In the later one, power rings are formed for I/O
cells and trunks are constructed between core power ring
and power pads. Top to bottom approach is used for the power analysis
of flatten design while bottom up approach is suitable for macros.

The
power information can be obtained from the front end design. The
synthesis tool reports static power information. Dynamic power can be
calculated using Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF)
file in conjunction with RTL description and test bench. Exhaustive
test coverage is required for efficient calculation of peak power. This
methodology is depicted in Figure (1).

For
the hierarchical design budgeting has to be carried out in front end.
Power is calculated from each block of the design. Astro works on
flattened netlist. Hence here top to bottom approach can be used.
JupiterXT can work on hierarchical designs. Hence bottom up approach
for power analysis can be used with JupiterXT. IR drops are not found
in floor planning stage. In placement stage rails are get connected
with power rings, straps, trunks. Now IR drops comes into picture and
improper design of power can lead to large IR drops and core may not get sufficient power.

Figure (1) Power Planning methodology

Below are the calculations for flattened design of the SAMM. Only static power reported by the Synthesis tool (Design Compiler) is used instead of dynamic power.

The number of the core power pad required for each side of the chip

= total core power / [number of side*core voltage*maximum allowable current for a I/O pad]

= 236.2068mW/ [4 * 1.08 V * 24mA] (Considering design SAMM)

= 2.278

~ 2

Therefore for each side of the chip 2 power pads (2 VDD and 2 VSS) are added.

Total dynamic core current (mA)

= total dynamic core power / core voltage

= 236.2068mW / 1.08V

= 218.71 mA

Core PG ring width

= (Total dynamic core current)/ (No. of sides * maximum current density of the metal layer used (Jmax) for PG ring)
=218.71 mA/(4*49.5 mA/μm)
~1.1 μm
~2 μm