原创 核心板测试程序(verilog)

简单的测试程序，大家做个参考。适用与XC3S500E＋USB2.0 核心板。

XC3S500E 核心板，只有按键的管教定义稍有不同，改一下就行。

//  top.v                       顶层文件

//---------------------------top.v  begin------------------------------------//

module top(  key, led, sys_clk, sys_rstb,extio,
                    usb_scl,usb_sda
                );
    input key;
    output [1:0] led;
    input sys_clk;
    input sys_rstb;
  output extio;
  inout usb_scl;
  inout usb_sda;

assign usb_scl = 1'bz;
assign usb_sda = 1'bz;

reg [24:0] count;
always @(posedge sys_clk or negedge sys_rstb)
if(!sys_rstb)
  count <= 0;
else
  count <= count +1;

reg led_d;
always @(posedge sys_clk or negedge sys_rstb)
if(!sys_rstb)
  led_d <= 0;
else if(count == 1)
  led_d <= ~led_d;
 
assign led = {~key,led_d};
assign extio = key & led_d;
endmodule

//---------------------------top.v end------------------------------------//

// top.ucf                        管脚约束文件

//---------------------------top.ucf begin------------------------------------//

NET "sys_clk"       LOC="P80" |IOSTANDARD=LVCMOS33 ;
NET "sys_rstb"      LOC="P110" |IOSTANDARD=LVCMOS33 ;

NET "key"         LOC="P32" |IOSTANDARD=LVCMOS33 | PULLUP;
NET "led{0}"      LOC="P102" |IOSTANDARD=LVCMOS33 ;
NET "led{1}"      LOC="P100" |IOSTANDARD=LVCMOS33  ;
NET "extio"      LOC="P2" |IOSTANDARD=LVCMOS33 ;

NET "usb_scl"      LOC="P112" |IOSTANDARD=LVCMOS33 ;
NET "usb_sda"      LOC="P109" |IOSTANDARD=LVCMOS33 ;

//---------------------------top.ucf end------------------------------------//