原创 关于ACEX1K EP1K30TC144-3的配置资料

2010-4-25 15:52 2966 2 3 分类: FPGA/CPLD

   关于ACEX1K  EP1K30TC144-3的配置资料


 


 


    最近在学习关于单片机配置FPGA的知识,看了一些英文资料,现摘抄整理出来,从中可以了解FPGA配置的原理和流程.


----------------------------


Configuration &Operation<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />


The ACEX 1K architecture supports several configuration schemes. This section summarizes the device operating modes and available device configuration schemes.


Operating Modes


The ACEX 1K architecture uses SRAM configuration elements that require configuration data to be loaded every time the circuit powers up.The process of physically loading the SRAM data into the device is called configuration. Before configuration, as VCC rises, the device initiates a Power-On Reset (POR). This POR event clears the device and prepares it for configuration. The ACEX 1K POR time does not exceed 50 μs.


  When configuring with a configuration device, refer to the relevant configuration device data sheet for POR timing information.


During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. Before and during configuration, all I/O pins (except dedicated inputs, clock, or configuration pins) are pulled high by a weak pull-up resistor. Together, the configuration and initialization processes are called command mode; normal device operation is called user mode.SRAM configuration elements allow ACEX 1K devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, re-initializing the device, and resuming user-mode operation. The entire reconfiguration process requires less than 40 ms and can be used to reconfigure an entire system dynamically. In-field upgrades can be performed by distributing


new configuration files.


Configuration Schemes


The configuration data for an ACEX 1K device can be loaded with one of five configuration schemes (see Table 59), chosen on the basis of the target application. An EPC16, EPC2, EPC1, or EPC1441 configuration device, intelligent controller, or the JTAG port can be used to control the


configuration of a ACEX 1K device, allowing automatic configuration on system power-up. Multiple ACEX 1K devices can be configured in any of the five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Additional APEX 20K, APEX 20KE, FLEX 10K, FLEX 10KA, FLEX 10KE, ACEX 1K,


and FLEX 6000 devices can be configured in the same serial chain.


 


完整资料点击下载:pdf

文章评论1条评论)

登录后参与讨论

用户377235 2013-5-22 11:01

很好
相关推荐阅读
用户264910 2010-04-27 06:45
Wire 与 Reg 的区别(Verilog)
数据类型 Wire 与 Reg 的区别,以下是网上资料的整理(不知道是不是官方的解释,学习ing...):====================================There are t...
用户264910 2010-04-26 00:28
基于FPGA/NiosII的等精度数字频率计的设计
基于FPGA/NiosII的等精度数字频率计的设计有以下特点:    1. CPU并行处理   32位软核处理器 NiosII 、处理速度为75MHZ         标准计数器,处理速度为100MH...
用户264910 2010-04-25 21:40
触摸式鼠标的设计实现
    利用CYPRESS的平台,做项目开发,可以节省好多时间(深有体会)。利用CY8C2489C这款IC,可以实现触摸式 USB 鼠标。通过初步硬件调试,发现效果还不错,基本上实现了USB 鼠标的相...
用户264910 2010-04-25 15:49
Avalon总线学习
Avalon总线具有以下基本特点:   ● 所有外设的接口与Avalon总线时钟同步,不需要复杂的握手/应答机制。这样就简化了Avalon总 线的时序行为,而且便于集成高速外设。Avalon总线以及整...
用户264910 2010-04-25 10:58
USB 驱动开发板
在产品设计开发中,常常感叹各种需要加入各种各样的驱动(包括加入硬件驱动IC和驱动程序的编写)。常常感到心有余而力不足啊。比如说,USB驱动。在这USB横行的年代,过去以往的串口已经退出历史的舞台了。虽...
我要评论
1
2
关闭 站长推荐上一条 /2 下一条