原创 Wire 与 Reg 的区别(Verilog)

数据类型 Wire 与 Reg 的区别，以下是网上资料的整理(不知道是不是官方的解释，学习ing...）：

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There are two main groups of data types: the register data types and the net data types.(others only include: parameter, specparam, event ).

The net data types represent physical connections between structural entities,
such as gates. A net does not store a value (except for the trireg net).

A register is an abstraction of a data storage element.

A register stores a value from one assignment to the next.
An assignment statement in a procedure acts as a trigger that changes the value in the data storage element.
The default initialization value for a reg data type is the unknown value, x.
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Register data types are used as variables in procedural blocks.
Registers store logic values only (no logic strength).
A register data type must be used when the signal is on the left-hand side of a procedural assignment. (quartus II 编译时常见的报错信息）
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Net data types connect structural components together.
Nets transfer both logic values and logic strengths.
A net data type must be used when:
A signal is driven by the output of some device.
A signal is also declared as an input port or inout port.
A signal is on the left-hand side of a continuous assignment.

在线学习Verilog:  http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html