原创 SDRAM+XCL

     最近调试的SDRAM，问题多多。归结一下。

mhs文件内容：

PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 66666667
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT mpmc_0_SDRAM_CS_n_pin = sdram_cs_n, DIR = O
 PORT mpmc_0_SDRAM_Clk_pin = sdram_clk, DIR = O
 PORT mpmc_0_SDRAM_CE_pin = sdram_ce, DIR = O
 PORT mpmc_0_SDRAM_RAS_pin = sdram_ras, DIR = O
 PORT mpmc_0_SDRAM_CAS_pin = sdram_cas, DIR = O
 PORT mpmc_0_SDRAM_WE_pin = sdram_we, DIR = O
 PORT mpmc_0_SDRAM_BankAddr_pin = sdram_ba, DIR = O, VEC = [1:0]
 PORT mpmc_0_SDRAM_Addr_pin = sdram_addr, DIR = O, VEC = [12:0]
 PORT mpmc_0_SDRAM_DQ = mpmc_0_SDRAM_DQ, DIR = IO, VEC = [15:0]
 PORT mpmc_0_SDRAM_DM_pin = sdram_dm, DIR = O, VEC = [1:0]

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 7.20.d
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 64
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 64
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xc4000000
 PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff
 PARAMETER C_DCACHE_BASEADDR = 0xc4000000
 PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 BUS_INTERFACE IXCL = microblaze_0_IXCL
 BUS_INTERFACE DXCL = microblaze_0_DXCL
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_66_6667MHzDCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_66_6667MHzDCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_66_6667MHzDCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE BRAM_PORT = dlmb_port
 BUS_INTERFACE SLMB = dlmb
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER HW_VER = 1.00.g
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 2.00.a
 PORT Slowest_sync_clk = clk_66_6667MHzDCM0
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
END

BEGIN mpmc
 PARAMETER INSTANCE = mpmc_0
 PARAMETER HW_VER = 5.04.a
 PARAMETER C_MEM_PARTNO = CUSTOM
 PARAMETER C_MEM_TYPE = SDRAM
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_PIM0_BASETYPE = 1
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_USE_STATIC_PHY = 0
 PARAMETER C_STATIC_PHY_RDEN_DELAY = 8
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 15000
 PARAMETER C_PI0_RD_FIFO_MEM_PIPELINE = 1
 PARAMETER C_PI0_RD_FIFO_APP_PIPELINE = 1
 PARAMETER C_PI0_WR_FIFO_MEM_PIPELINE = 1
 PARAMETER C_PI0_WR_FIFO_APP_PIPELINE = 1
 PARAMETER C_PI0_ADDRACK_PIPELINE = 1
 PARAMETER C_WR_DATAPATH_TML_PIPELINE = 1
 PARAMETER C_MEM_PART_DATA_DEPTH = 1
 PARAMETER C_MEM_PART_DATA_WIDTH = 16
 PARAMETER C_MEM_PART_NUM_BANK_BITS = 2
 PARAMETER C_MEM_PART_NUM_ROW_BITS = 13
 PARAMETER C_MEM_PART_NUM_COL_BITS = 10
 PARAMETER C_MEM_PART_CAS_A_FMAX = 133
 PARAMETER C_MEM_PART_CAS_A = 3
 PARAMETER C_MEM_PART_TRRD = 15000
 PARAMETER C_MEM_PART_TRCD = 20000
 PARAMETER C_MEM_PART_TWR = 15000
 PARAMETER C_MEM_PART_TREFI = 7812500
 PARAMETER C_MEM_PART_TRFC = 66000
 PARAMETER C_MEM_PART_TRP = 20000
 PARAMETER C_MEM_PART_TRC = 66000
 PARAMETER C_MEM_PART_TRASMAX = 120000000
 PARAMETER C_MEM_PART_TRAS = 44000
 PARAMETER C_PIM1_BASETYPE = 0
 PARAMETER C_XCL0_B_IN_USE = 1
 PARAMETER C_MPMC_BASEADDR = 0xC4000000
 PARAMETER C_MPMC_HIGHADDR = 0xC7FFFFFF
 PARAMETER C_MPMC_CTRL_BASEADDR = 0x20000000
 PARAMETER C_MPMC_CTRL_HIGHADDR = 0x2000ffff
 BUS_INTERFACE MPMC_CTRL = mb_plb
 BUS_INTERFACE XCL0 = microblaze_0_IXCL
 BUS_INTERFACE XCL0_B = microblaze_0_DXCL
 PORT MPMC_Rst = sys_bus_reset
 PORT MPMC_Clk0 = clk_66_6667MHzDCM0
 PORT SDRAM_CS_n = sdram_cs_n
 PORT SDRAM_Clk = sdram_clk
 PORT SDRAM_WE_n = sdram_we
 PORT SDRAM_CAS_n = sdram_cas
 PORT SDRAM_RAS_n = sdram_ras
 PORT SDRAM_CE = sdram_ce
 PORT SDRAM_BankAddr = sdram_ba
 PORT SDRAM_Addr = sdram_addr
 PORT SDRAM_DQ = mpmc_0_SDRAM_DQ
 PORT SDRAM_DM = sdram_dm
 PORT MPMC_Clk_Mem = clk_133_3333MHz
 PORT MPMC_DCM_PSEN = Static_Phy_DCM_PSEN
 PORT MPMC_DCM_PSINCDEC = Static_Phy_DCM_PSINCDEC
 PORT MPMC_DCM_PSDONE = Static_Phy_DCM_PSDONE
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_module_0
 PARAMETER HW_VER = 1.00.d
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKOUT_PHASE_SHIFT = VARIABLE_POSITIVE
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_PHASE_SHIFT = 0
 PARAMETER C_CLK180_BUF = FALSE
 PARAMETER C_CLKIN_PERIOD = 7.5
 PARAMETER C_CLKFB_BUF = FALSE
 PORT RST = sys_rst_s
 PORT CLKIN = clk_133_3333MHz
 PORT CLKFB = SDR_SDRAM_MPMC_Clk_Mem
 PORT CLK0 = SDR_SDRAM_MPMC_Clk_Mem
 PORT PSDONE = Static_Phy_DCM_PSDONE
 PORT LOCKED = dcm_module_0_LOCKED
 PORT PSEN = Static_Phy_DCM_PSEN
 PORT PSCLK = clk_133_3333MHz
 PORT PSINCDEC = Static_Phy_DCM_PSINCDEC
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLKIN_FREQ = 66666667
 PARAMETER C_CLKOUT0_FREQ = 133333333
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER HW_VER = 3.02.a
 PARAMETER C_CLKOUT1_FREQ = 66666667
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_133_3333MHz
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
 PORT CLKOUT1 = clk_66_6667MHzDCM0
END

debug结果如下：

  关闭cache. 请问：关闭cache还能往SDRAM写入数据吗？

  debug下会发现：

       Xuint32 i;
    u32 *Addr;
    Xuint32 value;
   
    Addr = XPAR_MPMC_0_MPMC_BASEADDR;

      for(i= 0; i<2048;i=i+1)
      {
          Addr= i      }
      
      for(i= 0; i<2048;i=i+1)
      {
         value = Addr;     
      }