原创 数据缓存操作的一些问题

Data Cache Operation
             The caching policy used by the MicroBlaze data cache, write-back or write-through, is determined by the parameter C_DCACHE_USE_WRITEBACK. When this parameter is set, a write-back protocol is implemented, otherwise write-through is implemented. However, when configured with an MMU (C_USE_MMU > 1, C_AREA_OPTIMIZED = 0, C_DCACHE_USE_WRITEBACK = 1), the caching policy in virtual mode is determined by the W storage attribute in the TLB entry, whereas write-back is used in real mode.
            With the write-back protocol, a store to an address within the cacheable range always updates the cached data. If the target address word is not in the cache (that is, the access is a cache-miss), and the location in the cache contains data that has not yet been written to memory (the cache location is dirty), the old data is written over the data CacheLink (DXCL) to external memory before updating the cache with the new data. If an entire cache line needs to be written, a burst cache line write is used, otherwise single word writes are used. For byte or halfword stores, in case of a cache-miss, the address is first requested over the data CacheLink, while a word store only updates the cache.？？？
          With the write-through protocol, a store to an address within the cacheable range generates an equivalent byte, halfword, or word write over the data CacheLink to external memory. The write also updates the cached data if the target address word is in the cache (that is, the write is a cache-hit). A write cache-miss does not load the associated cache line into the cache.
          Provided that the cache is enabled a load from an address within the cacheable range triggers a check to determine if the requested data is currently cached. If it is (that is, on a cache-hit) the requested data is retrieved from the cache. If not (that is, on a cache-miss) the address is requested over the data CacheLink, and the processor pipeline stalls until the cache line associated to the requested address is returned from the external memory controller.

       当我C_DCACHE_USE_WRITEBACK=1，也就是说选择write-back协议时，sdram读写为正确的。