Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register and the corresponding bit in the HcInterruptEnable register is set and the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus.
Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit unchanged. On read, the current value of this register is returned.
3 | 3 | 2 |
|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 9 |
|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
M I E
| O C | reserved |
| R H S C | F N O | U E | R D | S F | W D H | S O | ||
Figure 7-5: HcInterruptEnable Register
|
| Read/Write |
| |
Key | Reset | HCD | HC | Description |
SO | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to Scheduling Overrun. |
WDH | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to HcDoneHead Writeback. |
SF | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to Start of Frame. |
RD | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to Resume Detect. |
UE | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to Unrecoverable Error. |
FNO | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to Frame Number Overflow. |
RHSC | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to Root Hub Status Change. |
OC | 0b | R/W | R | 0 - Ignore 1 - Enable interrupt generation due to Ownership Change. |
MIE | 0b | R/W | R | A ‘0’ written to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as a Master Interrupt Enable. |
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