//搞了一天总算将单片机程序改成了verilog代码
module song(clk,rst,speaker);
input clk;
input rst;
output speaker;
reg clk1MHz; //分频产生1MHz的脉冲
reg speaker;
reg delay;
reg [25:0]cnt1,cnt3;
reg [15:0]cnt2;
reg [2:0]cnt4;
reg [4:0]note;
reg [5:0]state;
reg [16:0]divider;
wire carry;
assign carry=(divider==65536); //16位计数器
always @ (posedge clk)
begin
if(!rst)
begin
cnt1<=0;
end
else
begin
if(cnt1==25)
begin
cnt1<=0;
clk1MHz<=~clk1MHz; //1MHz分频部分
end
else
begin
cnt1<=cnt1+1'b1;
end
end
end
always @ (posedge clk1MHz) //音符频率
begin
if(carry)
divider=cnt2;
else
divider=divider+1'b1;
end
always @ (posedge carry)
begin
speaker=~speaker;
end
always @ (posedge clk)
begin
case(note)
0 : begin cnt2=16'hf242; end
1 : begin cnt2=16'hf3c1; end
2 : begin cnt2=16'hf517; end
3 : begin cnt2=16'hf5b6; end
4 : begin cnt2=16'hf6d0; end
5 : begin cnt2=16'hf7d1; end
6 : begin cnt2=16'hf8b6; end
7 : begin cnt2=16'hf921; end
8 : begin cnt2=16'hf9e1; end
9 : begin cnt2=16'hfa8c; end
10 : begin cnt2=16'hfad8; end
11 : begin cnt2=16'hfb68; end
12 : begin cnt2=16'hfbe9; end
13 : begin cnt2=16'hfc5b; end
14 : begin cnt2=16'hfc8f; end
15 : begin cnt2=16'hfcee; end
16 : begin cnt2=16'hfd44; end
17 : begin cnt2=16'hfd6b; end
18 : begin cnt2=16'hfdb4; end
19 : begin cnt2=16'hfdf4; end
20 : begin cnt2=16'hfe2d; end
default : begin cnt2=16'bx ; end
endcase
end
always @ (posedge clk)
begin
if(!rst)
begin
cnt3<=0;
end
else if(cnt3==6249999)
begin
delay<=~delay; //产生4Hz脉冲
cnt3<=0;
end
else
begin
cnt3<=cnt3+26'b1;
end
end
always @ (posedge delay)
begin
if(!rst)
begin
state<=0;
cnt4<=0;
end
else
begin
case(state)
0 : begin //歌曲《世上只有妈妈好》的曲谱
note<=19;
if(cnt4==2) //3个节拍
begin
cnt4<=0;
state<=1;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
1 : begin
note<=18; //1个节拍
state<=2;
end
2 : begin
note<=16;
if(cnt4==1) //2个节拍
begin
cnt4<=0;
state<=3;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
3 : begin
note<=18;
if(cnt4==1) //2个节拍
begin
cnt4<=0;
state<=4;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
4 : begin
note<=20;
if(cnt4==1) //2个节拍
begin
cnt4<=0;
state<=5;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
5 : begin //1个节拍
note<=19;
state<=6;
end
6 : begin //1个节拍
note<=18;
state<=7;
end
7 : begin
note<=19; //4个节拍
if(cnt4==3)
begin
cnt4<=0;
state<=8;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
8 : begin //2个节拍
note<=16;
if(cnt4==1)
begin
cnt4<=0;
state<=9;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
9 : begin //1个节拍
note<=18;
state<=10;
end
10 : begin //1个节拍
note<=19;
state<=11;
end
11 : begin //2个节拍
note<=18;
if(cnt4==1)
begin
cnt4<=0;
state<=12;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
12 : begin
note<=16;
if(cnt4==1) //2个节拍
begin
cnt4<=0;
state<=13;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
13 : begin
note<=14;
state<=14;
end
14 : begin
note<=12;
state<=15;
end
15 : begin
note<=18;
state<=16;
end
16 : begin
note<=16;
state<=17;
end
17 : begin
note<=15;
if(cnt4==3)
begin
cnt4<=0;
state<=18;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
18 : begin
note<=15;
if(cnt4==2)
begin
cnt4<=0;
state<=19;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
19 : begin
note<=16;
state<=20;
end
20 : begin
note<=18;
if(cnt4==1)
begin
cnt4<=0;
state<=21;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
21 : begin
note<=18;
state<=22;
end
22 : begin
note<=19;
state<=23;
end
23 : begin
note<=16;
if(cnt4==1)
begin
cnt4<=0;
state<=24;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
24 : begin
note<=15;
if(cnt4==1)
begin
cnt4<=0;
state<=25;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
25 : begin
note<=14;
if(cnt4==3)
begin
cnt4<=0;
state<=26;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
26 : begin
note<=18;
if(cnt4==2)
begin
cnt4<=0;
state<=27;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
27 : begin
note<=16;
state<=28;
end
28 : begin
note<=15;
state<=29;
end
29 : begin
note<=14;
state<=30;
end
30 : begin
note<=12;
state<=31;
end
31 : begin
note<=14;
state<=32;
end
32 : begin
note<=11;
if(cnt4==5)
begin
cnt4<=0;
state<=0;
end
else
begin
cnt4<=cnt4+3'b1;
end
end
default : begin state<=0; end
endcase
end
end
endmodule
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用户377235 2013-5-15 08:45
用户1668396 2012-10-26 09:35