原创 Discussions on IP (Part 4)

2013-9-4 18:36 1265 7 7 分类: 消费电子

Part 1 focused on the concept of IP being a partnership between the IP supplier and the user. Part 2 asked whether IP is too complex for start-ups. In Part 3, we looked at IP and sub-systems.


Taking part in this discussion are: Mike Gianfagna, vice president of corporate marketing at Atrenta; Warren Savage, CEO of IPextreme; John Koeter, vice president of marketing at the solutions group of Synopsys; and Chris Rowen, Cadence Fellow and CTO of Tensilica.


Brian Bailey: We talked about standards as they relate to the hardware interfaces. What about standards within IP itself—how we package them, how we ship them, how they integrate?


John Koeter: There's a lot of standards such as GDSII, LEF, .lib files, Verilog...


Warren Savage: Those are all driven from EDA compatibility. They're not functional in any form...


Brian Bailey: We've got IP-XACT, System RTL, but that's about it at the moment, isn't it?


Warren Savage: Somebody from one of the large semiconductor companies said to me, where are the standards on deliverables? We work with the GSA IP working group, and it's a topic that comes up. But when you talk about deliverables, it doesn't seem like anyone's doing anything dramatically different from the other guys. It seems like it's not that big of a problem, although people would love it to be checklist-based with a standard road map.


Mike Gianfagna: That's one of the things that is on our road map. We've done a lot of work verifying the completeness of IP—now what about packaging, creating a package that allows it to be reusable? How do you leverage what you know to the next step? That is something that we're working on. But is there a standard out there? No.


Chris Rowen: The hardware side has turned out to be easier than the software side. I was surprised in the evolution of Tensilica that we so easily satisfied the expectations of the hardware teams in terms of deliverables. With soft IP, if you're delivering RTL and test benches and verification environments and exhaustive documentation and scripts for every known CAD tool, you're in pretty good shape. But on the software side in terms of compilers, debuggers, 14 different RTOSes, all these different graphical user interfaces, 10 different debug ports—it's an unbounded number of things. Getting people to stabilise their expectations on the software side is actually taking longer. That's the beauty of software; it doesn't have any hard limits in terms of what people expect it to be and do. They expect it to do anything, anytime, anywhere, and support the beta standard that was never thought of at the time that we originally signed the deal.


Brian Bailey: Two of our panelists are IP developers now within large EDA companies. Does that create any problems?


Chris Rowen: I think the only answer I can make at this point is it's too soon to know.


John Koeter: There are firewalls where appropriate. Our services organisation, field organisation, and our tools work with ARM cores—hardening ARM cores, often using or perhaps using ARM libraries, or memories. We have firewalled that off from any access to the IP groups. We don't allow certain groups to talk to other groups, because there may be a conflict of interest. It is something you have to be good at.


Chris Rowen: Right, and I think that the situation for Tensilica is really the dual of what John says—the EDA industry has worked out some principles for handling this kind of situation and they seem to be allowing customers to be successful, and that's the important thing.


 

Brian Bailey

EE Times

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