原创 (ZT)430资料※六

十二、 Flash存储器

#define FCTL1              (0x0128)  /* FLASH Control 1 */

#define FCTL2             (0x<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />012A)  /* FLASH Control 2 */

#define FCTL3              (0x012C)  /* FLASH Control 3 */

<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

#define FRKEY               (0x9600)  /* Flash key returned by read */

#define FWKEY               (0xA500)  /* Flash key for write */

#define FXKEY               (0x3300)  /* for use with XOR instruction */

#define ERASE               (0x0002)  /* Enable bit for Flash segment erase */

#define MERAS               (0x0004)  /* Enable bit for Flash mass erase */

#define WRT                 (0x0040)  /* Enable bit for Flash write */

#define BLKWRT              (0x0080)  /* Enable bit for Flash segment write */

#define SEGWRT              (0x0080)  /* old definition */ /* Enable bit for Flash segment write */

#define FN0                 (0x0001)  /* Devide Flash clock by 1 to 64 using FN0 to FN5 according to: */

#define FN1                 (0x0002)  /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */

#define FN2                 (0x0004) 

#define FN3                 (0x0008) 

#define FN4                 (0x0010)

#define FN5                 (0x0020)

#define FSSEL0              (0x0040)  /* Flash clock select 0 */        /* to distinguish from USART SSELx */

#define FSSEL1              (0x0080)  /* Flash clock select 1 */

#define FSSEL_0             (0x0000)  /* Flash clock select: 0 - ACLK */

#define FSSEL_1             (0x0040)  /* Flash clock select: 1 - MCLK */

#define FSSEL_2             (0x0080)  /* Flash clock select: 2 - SMCLK */

#define FSSEL_3             (0x00C0)  /* Flash clock select: 3 - SMCLK */

#define BUSY                (0x0001)  /* Flash busy: 1 */

#define KEYV                (0x0002)  /* Flash Key violation flag */

#define ACCVIFG             (0x0004)  /* Flash Access violation flag */

#define WAIT                (0x0008)  /* Wait flag for segment write */

#define LOCK                (0x0010)  /* Lock bit: 1 - Flash is locked (read only) */

#define EMEX                (0x0020)  /* Flash Emergency Exit */

十三、比较器

#define CACTL1             (0x0059)  /* Comparator A Control 1 */

#define CACTL2             (0x005A)  /* Comparator A Control 2 */

#define CAPD               (0x005B)  /* Comparator A Port Disable */

#define CAIFG               (0x01)    /* Comp. A Interrupt Flag */

#define CAIE                (0x02)    /* Comp. A Interrupt Enable */

#define CAIES               (0x04)    /* Comp. A Int. Edge Select: 0:rising / 1:falling */

#define CAON                (0x08)    /* Comp. A enable */

#define CAREF0              (0x10)    /* Comp. A Internal Reference Select 0 */

#define CAREF1              (0x20)    /* Comp. A Internal Reference Select 1 */

#define CARSEL              (0x40)    /* Comp. A Internal Reference Enable */

#define CAEX                (0x80)    /* Comp. A Exchange Inputs */

#define CAREF_0             (0x00)    /* Comp. A Int. Ref. Select 0 : Off */

#define CAREF_1             (0x10)    /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */

#define CAREF_2             (0x20)    /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */

#define CAREF_3             (0x30)    /* Comp. A Int. Ref. Select 3 : Vt*/

#define CAOUT               (0x01)    /* Comp. A Output */

#define CAF                 (0x02)    /* Comp. A Enable Output Filter */

#define P2CA0               (0x04)    /* Comp. A Connect External Signal to CA0 : 1 */

#define P2CA1               (0x08)    /* Comp. A Connect External Signal to CA1 : 1 */

#define CACTL24             (0x10)

#define CACTL25             (0x20)

#define CACTL26             (0x40)

#define CACTL27             (0x80)

#define CAPD0               (0x01)    /* Comp. A Disable Input Buffer of Port Register .0 */

#define CAPD1               (0x02)    /* Comp. A Disable Input Buffer of Port Register .1 */

#define CAPD2               (0x04)    /* Comp. A Disable Input Buffer of Port Register .2 */

#define CAPD3               (0x08)    /* Comp. A Disable Input Buffer of Port Register .3 */

#define CAPD4               (0x10)    /* Comp. A Disable Input Buffer of Port Register .4 */

#define CAPD5               (0x20)    /* Comp. A Disable Input Buffer of Port Register .5 */

#define CAPD6               (0x40)    /* Comp. A Disable Input Buffer of Port Register .6 */

#define CAPD7               (0x80)    /* Comp. A Disable Input Buffer of Port Register .7 */

十四、中断向量

#define BASICTIMER_VECTOR       (0 * 2u)  /* 0xFFE0 Basic Timer */

#define PORT2_VECTOR             (1 * 2u)  /* 0xFFE2Port 2 */

#define PORT1_VECTOR             (4 * 2u)  /* 0xFFE8Port 1 */

#define TIMERA1_VECTOR          (5 * 2u)  /* 0xFFEA Timer A CC1-2, TA */

#define TIMERA0_VECTOR           (6 * 2u)  /* 0xFFEC Timer A CC0 */

#define WDT_VECTOR              (10 * 2u) /* 0xFFF4 Watchdog Timer */

#define COMPARATORA_VECTOR  (11 * 2u) /* 0xFFF6 Comparator A */

#define NMI_VECTOR               (14 * 2u) /* 0xFFFC Non-maskable */

#define RESET_VECTOR             (15 * 2u) /* 0xFFFE Reset [Highest Priority] */