原创 ADS7818控制程序 C程序 Verilog程序

//************************AVR单片机 C程序*****************************
//ADS7818采用SPI模式采样

#define CLK_SET  PORTC|=(1<<6)    
#define CLK_CLI  PORTC&=~(1<<6)

#define CONV_SET  PORTC|=(1<<5)
#define CONV_CLI  PORTC&=~(1<<5)


//****************************ADS7818采样程序********************************
//晶振16M
//ADS7818采用SPI模式采样

unsigned int ADS7818(void)
{
 unsigned int ADdata=0;
 unsigned char i;
 
 
  CONV_CLI;           //conv低
  CLK_SET;   //1clk   //clk高
  _NOP();
  CLK_CLI;             //clk低
  _NOP();
  CLK_SET;   //2clk     //clk高
   _NOP();
 
  for(i=0;i<12;i++)
  {
   CLK_CLI;             //clk低
   _NOP();
   CLK_SET;             //clk高
   _NOP();
  
  
   ADdata=ADdata<<1;
   if(PINC&0x80)
    {
     ADdata|=0x0001;
    }
   else
    {
     ADdata&=0xFFFE;
    }
 
  
  }
   CLK_CLI;            //clk低
   _NOP();
  CLK_SET;  //15 clk   //clk高
  _NOP();
  CLK_CLI;             //clk低
  _NOP();
  CLK_SET;  //16 clk   //clk高
  _NOP();
  CLK_CLI;             //clk拉低
  _NOP();
  CONV_SET; //CONV拉高
  _NOP();    //至少保持350ns
  _NOP();
  _NOP();
  _NOP();
  _NOP();
  _NOP();
  _NOP();
  _NOP();
  _NOP();
  ADdata=ADdata&0x0FFF;
 return ADdata;
}



//**********************verilog语言控制ADS7818*********************



//ADS7818采用DSP模式采样
/************************************************************************************
**读取ADS7818数据
**clk为50M

***************************************************************************************/
module read_7818(clk,rst,CLK_7818,DATA_7818,CONV_7818,AD_result);
 input clk;
 input rst;
 input DATA_7818;

 output CLK_7818;
 output CONV_7818;
 output [11:0]AD_result;
 


 reg CLK_7818;
 reg CONV_7818;
 reg [11:0]AD_result;



reg [1:0]num_80ns;
reg clk_80ns;
//*******************************分频程序**********************
always @(posedge clk)
 begin
  if(num_80ns==2'd1)
     begin
       num_80ns=2'd0;
       clk_80ns=~clk_80ns;
     end
  else
     begin
      num_80ns=num_80ns+1'b1;
     end

 end


//************************************控制时序****************************

 reg [5:0]state_7818;
 reg [11:0]AD_reg;             //采样数据缓存

always @(posedge clk_80ns or negedge rst)
 begin
  if(!rst)
    begin
        state_7818<=6'd0;
 
    end
  else
    begin
       case(state_7818)
          0:                        
            begin
               CLK_7818<=1'b0;
               state_7818<=6'd1;
            end
          1:                        //clk up 1
            begin
               CLK_7818<=1'b1;
               CONV_7818<=1'b1;
               state_7818<=6'd2;
   
            end      
          2:
            begin
              
               CLK_7818<=1'b0;           
               state_7818<=6'd3;
            end      
          3:                       //clk up 2 
            begin
             
               CLK_7818<=1'b1; 
               AD_reg[11]<=DATA_7818;   
               state_7818<=6'd4;
            end
          4:
            begin
              
               CLK_7818<=1'b0;           
               state_7818<=6'd5;
            end
          5:                       //clk up 3 
            begin
               CLK_7818<=1'b1;
               AD_reg[10]<=DATA_7818;           
               state_7818<=6'd6;
            end
          6:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd7;

            end
          7:                     //clk up 4
            begin
               CLK_7818<=1'b1; 
               AD_reg[9]<=DATA_7818;
               state_7818<=6'd8;
            end
          8:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd9;
            end
          9:                     //clk up 5
            begin
               CLK_7818<=1'b1;  
               AD_reg[8]<=DATA_7818;
               state_7818<=6'd10;
            end
          10:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd11;
            end
          11:                     //clk up 6
            begin
               CLK_7818<=1'b1;  
               AD_reg[7]<=DATA_7818;
               state_7818<=6'd12;
            end
          12:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd13;
            end
          13:                     //clk up 7
            begin
               CLK_7818<=1'b1;  
               AD_reg[6]<=DATA_7818;
               state_7818<=6'd14;
            end
          14:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd15;
            end
          15:                     //clk up 8
            begin
               CLK_7818<=1'b1;  
               AD_reg[5]<=DATA_7818;
               state_7818<=6'd16;
            end
          16:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd17;
            end
          17:                     //clk up 9
            begin
               CLK_7818<=1'b1;  
               AD_reg[4]<=DATA_7818;
               state_7818<=6'd18;
            end
          18:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd19;
            end
          19:                     //clk up 10
            begin
               CLK_7818<=1'b1;  
               AD_reg[3]<=DATA_7818;
               state_7818<=6'd20;
            end
          20:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd21;
            end
          21:                     //clk up 11
            begin
               CLK_7818<=1'b1;  
               AD_reg[2]<=DATA_7818;
               state_7818<=6'd22;
            end
          22:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd23;
            end
          23:                     //clk up 12
            begin
               CLK_7818<=1'b1;  
               AD_reg[1]<=DATA_7818;
               state_7818<=6'd24;
            end
          24:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd25;

            end
          25:                     //clk up  13
            begin
               CLK_7818<=1'b1;  
               AD_reg[0]<=DATA_7818;
               state_7818<=6'd26;
            end
          26:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd27;
            end
          27:                     //clk up  14
            begin
               CLK_7818<=1'b1;  
               state_7818<=6'd28;
            end
          28:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd29;
            end
          29:                     //clk up  15
            begin
               CLK_7818<=1'b1;  
               AD_result<=AD_reg;           //将采集的12位数据打入出输出
               state_7818<=6'd30;

            end
          30:
            begin
               CLK_7818<=1'b0;           
               state_7818<=6'd31;
            end
          31:                     //clk up  16
            begin
              
               CLK_7818<=1'b1;  
               CONV_7818<=1'b0;
               state_7818<=6'd0;
              
            end

          default:
            begin
            end

       endcase
    end

 end




endmodule