原创 FPGA--3数码管显示0-F

   通过分频计数，bt作为位选信号，se段选信号，经分频后对cot计数，实现0-F的显示，本实验选最后一位。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity xianshi is
  port(clk:in std_logic;
      se:out std_logic_vector(0 to 7);
      bt:out std_logic_vector(0 to 7);
      beer:out bit);
end xianshi;
architecture one of xianshi is
    signal clk1:std_logic;
    signal cnt:integer range 0 to 25000000;
    signal cot:integer range 0 to 15;
    begin
        beer<='1';
        process(clk)      --计数模块  
   begin
     if clk'event and clk='1' then
     if cnt=25000000 then
      cnt<=0;
      clk1<=not clk1;
     else
      cnt<=cnt + 1 ;
  end if ;
  end if ;
  end process;
   process(clk)      --计数模块  
   begin
     if clk1'event and clk1='1' then
     if cot=15 then
      cot<=0;
     else
      cot<=cot + 1 ;
  end if ;
  end if ;
  end process;
      process(cot)--duan    数据0亮
        begin
           case cot is
            when 0=>se<="00000011";bt<="11111110";--显示0  0位选

            when 1=>se<="10011111";bt<="11111110";--1
            when 2=>se<="00100101";bt<="11111110";--2
            when 3=>se<="00001101";bt<="11111110";--3
            when 4=>se<="10011001";bt<="11111110";--4
            when 5=>se<="01001001";bt<="11111110";--5
            when 6=>se<="01000001";bt<="11111110";--6
            when 7=>se<="00011111";bt<="11111110";--7
            when 8=>se<="00000001";bt<="11111110";--8
            when 9=>se<="00001001";bt<="11111110";--9
            when 10=>se<="00010001";bt<="11111110";--a
            when 11=>se<="11000001";bt<="11111110";--b
            when 12=>se<="01100011";bt<="11111110";--c
            when 13=>se<="10000101";bt<="11111110";--d
            when 14=>se<="01100001";bt<="11111110";--e
            when 15=>se<="01110001";bt<="11111110";--f
            when others=>se<="11111111";bt<="11111111";
            end case;
           end process;
        end one;