原创 FPGA_4电子时钟

把数码管玩了一下，想做个电子时钟，正在调试阶段以调试出来了，现已经测试完毕，相关代码如下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity shizhong is
  port(clk:in std_logic;
  beer:out bit;
  we:out std_logic_vector(7 downto 0);
  dout:out std_logic_vector(7 downto 0));
  end shizhong;
  architecture dianzi of shizhong is
    signal tsl:std_logic_vector(3 downto 0);
    signal tsh:std_logic_vector(3 downto 0);
    signal tml:std_logic_vector(3 downto 0);
    signal tmh:std_logic_vector(3 downto 0);    
    signal thl:std_logic_vector(3 downto 0);
    signal thh,data:std_logic_vector(3 downto 0);
    signal clk0,clk_1k,q1,q2,q3,q4:std_logic;
    signal count:integer range 0 to 25000000;
    component counter10 is
        port(clk:in std_logic;
              dout:out std_logic_vector(3 downto 0);
              c:out std_logic);
    end component;
  
     component counter6 is
        port(clk:in std_logic;
              dout:out std_logic_vector(3 downto 0);
              c:out std_logic);
    end component;
   
    component counter24 is
        port(clk:in std_logic;
              hl:out std_logic_vector(3 downto 0);
              hh:out std_logic_vector(3 downto 0));
    end component;
   
    component display is
        port( din:in std_logic_vector(3 downto 0);
              dout:out std_logic_vector(7 downto 0));
    end component;
   begin
   beer<='1';
  u1:counter10 port map(clk0,tsl,q1);--产生秒低位
  u2:counter6 port map(q1,tsh,q2);--产生秒高位
  u3:counter10 port map(q2,tml,q3);--产生分低位
  u4:counter6 port map(q3,tmh,q4);--产生时高低位
  u5:counter24 port map(q4,thl,thh);--产生时高位
 
    process (clk_1k)  --动态扫描显示，先位选 后送段选
    variable cnt2:std_logic_vector(3 downto 0);
     begin
    if clk_1k'event and clk_1k='1' then cnt2:=cnt2+1;
   if cnt2="0001" then
   we<="01111111";
   data<=thh;
   elsif cnt2="0010" then
   we<="10111111";
   data<=thl; 
   elsif cnt2="0011" then
   we<="11011111";
   data<="1010"; 
   elsif cnt2="0100" then
   we<="11101111";
   data<=tmh;
   elsif cnt2="0101" then
   we<="11110111";
   data<=tml;
  elsif cnt2="0110" then
   we<="11111011";
   data<="1011"; 
   elsif cnt2="0111" then
   we<="11111101";
   data<=tsh;
   elsif cnt2="1000" then
   we<="11111110";
   data<=tsl;
   cnt2:="0000";
   end if;
    end if;
    end process;
   process(clk)--产生1k的扫描信号
    variable cnt:integer range 0 to 25000;
      begin
       if rising_edge(clk) then cnt:=cnt+1;
         if cnt<12500 then clk_1k<='1';
          elsif cnt<25000 then clk_1k<='0';
          else cnt:=0;clk_1k<='0';
        end if;
        end if;
   end process;
    process(clk)      --  产生约1s时钟
    begin
     if clk'event and clk='1' then
     if count=25000000 then
      count<=0;
      clk0<=not clk0;
     else
      count<=count + 1 ;
         end if ;
  end if ;
   end process;
  u6:display port map(data,dout);--调用显示模块
  end dianzi;