原创 AT91SAM9261 firstboot 分析 startup.s

bsp源文件为：AT91SAM9261EK_CE6.0_Source_BSP_v1.0.3(从官方网站下载)
firstboot 是系统上电开始运行的第一个程序，而startup.s是firstboot 中运行的第一个程序。我将其简单注释，方便大家学习。
*********************************************************************
; Copyright (c) Microsoft Corporation.  All rights reserved.; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.

  INCLUDE kxarm.h   ;各种符号的宏定义，以便代码更简洁
  IMPORT main     ;导入外部函数
            ;INCLUDE与IMPORT为汇编伪操作
Mode_SVC   EQU    0x00000013
NoIntsMask  EQU    0x000000C0

;The stack begins at the end of the SRAM and goes top-down
AT91SAM9261EK_BOOTLOADER_STACK_BASE     EQU   0x00301FFC

;Romimage.exe needs a pTOC else the file .NB0 is not created
  EXPORT pTOC     ;导出pTOC,EXPORT为汇编伪操作

;------CPWAIT------------------------------------------------------------------
; Params: $Rd      : temporary read register
; Returns: nothing
; Effects: corrupts $Rd
; This macro is used to wait for coprocessor operations to complete.
;
; Ex:
;    CPWAIT r0
;------------------------------------------------------------------------------
  MACRO
  CPWAIT  $Rd

  mrc     p15, 0, $Rd, c2, c0, 0       ; arbitrary read of CP15
  mov     $Rd, $Rd                     ; wait for it (foward dependency)
  sub     pc, pc, #4                   ; branch to next instruction

  MEND
;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
;------------------------------------------------------------------------------
  AREA        reset, CODE, READONLY   ;ARM汇编伪指令,可查指令手册

;------------------------------------------------------------------------------
;- Define the entry point
;------------------------

  EXPORT __ENTRY
;__ENTRY

    STARTUPTEXT   
    LEAF_ENTRY __ENTRY

; 下面是微软官网上面的对LEAF_ENTRY的解释
; LEAF_ENTRY (ARM)
; This macro declares the beginning of a routine that does not require prolog code.

; LEAF_ENTRY Name[,
; [Section=]SectionName]

; Parameters
;  Name
;   The routine name.
;  SectionName
;   Optional. The name of the section where the entry appears. I
;    Defaults to .text.

; Return Values
; None.

; Remarks
; Name is in the global name space.

; A LEAF_ENTRY must have an associated ENTRY_END (ARM).

; Requirements
; OS Versions: Windows CE .NET 4.0 and later.
; Header: Kxarm.h.

;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors are read at address 0.
;- They absolutely requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping (what may be
;- dangerous in a final system). If an exception occurs before remap, this
;- would result in an infinite loop.
;------------------------------------------------------------------------------
resetini
    B           InitReset        ; reset
undefvec
    B           InitReset   ; Undefined Instruction
swivec
    B           InitReset           ; Software Interrupt
pabtvec
    B           pabtvec          ; Prefetch Abort
dabtvec
    B           dabtvec          ; Data Abort
rsvdvec
    B           rsvdvec          ; reserved
irqvec
    B           irqvec    ; IRQ : read the AIC
fiqvec
    B           fiqvec           ; FIQ

; This pointer on TOC structure must be declared after enter table
; else the first fourth byte are replace by this pointer

pTOC
  DCD 0      ;感兴趣的可以网上搜一下pTOC

; Init reset

InitReset
  ldr  r0, =0x00300000 - 4
  add  pc,pc,r0

; Put the CPU in Supervisor mode (SVC) and disable IRQ and FIQ interrupts.
; 设置cpu进入特权模式,同时禁止IRQ和FIQ中断
    ldr     r0, =(Mode_SVC :OR: NoIntsMask)
    msr     cpsr_c, r0

; Disable the MMU, caches, and write-buffer and flush.
; 禁能MMU,缓存,写缓冲和刷新
    ldr     r0, =0x2043             ; enable access to all coprocessors
                    ; ldr汇编伪指令,相当于 mov  r0, 0x2043
    mcr     p15, 0, r0, c15, c1, 0  ; Write Debug and Test Address Register
                    ; 在ARM926EJ-S Revision: r0p5 Technical Reference Manual
                    ; 没有给出Debug and Test Address Register的含义
                    ; 所以这条指令的具体意思不明白？
    CPWAIT  r0                      ; 宏指令CPWAIT是等待CP15更新完成,起到延时作用

    ldr     r0, =0x00000078         ; get a zero to turn things off (must write bits[6:3] as 1s)
    mcr     p15, 0, r0, c1, c0, 0   ; turn off MMU, I&D caches, and write buffer
    CPWAIT  r0                      ; 宏指令CPWAIT是等待CP15更新完成,起到延时作用

    mvn     r0, #0                  ; grant manager access to all domains
    mcr     p15, 0, r0, c3, c0, 0   ; 设置MMU中的域访问的控制属性,没有访问权限

; Icache enable and asynchronous clocking mode
; 指令缓存使能,设置为异步时钟模式
  mrc     p15,0,r6,c1,c0,0
  orr     r6,r6,#0xC0000000    ; C1[31:19]位是预留的，所以不明白这句含义?
  orr     r6,r6,#0x1000      ; 使能指令cache
  mcr     p15,0,r6,c1,c0,0

;  Set up a supervisor mode stack.设置堆栈指针
    ldr sp, =AT91SAM9261EK_BOOTLOADER_STACK_BASE

C_MAIN
; Jump to the C entrypoint.
    bl      main                 ; Jump to main.c::main(), never to return...
                   ; 跳转到main()函数执行,永远不再返回
STALL
    b      STALL
              
 EXPORT  Jump
Jump
  mov pc, r0    

            END
      
 END
*********************************************************************
虽然是参考了 ARM926EJ-S? Revision: r0p5 Technical Reference Manual
但其中还是有两条语句不明白，求高手指点。
这部分的内容主要是设置异常向量，禁用MMU和中断,然后跳转到main()函数执行。