原创 循环LED灯

2010-6-3 16:28 1885 2 2 分类: FPGA/CPLD
---     用FPGA点LED灯,初始状态LED灯熄灭,
   ---    第一次按键: LED灯闪烁;
   ---    第二次按键: LED灯恒亮;
   ---     第三次按键: LED灯恒灭;........
   ---     ......
   ---    如此循环下去。
   ---开发板一块,至少具备以下资源:
   --- A)按键2个,一个用于复位,一个用于控制灯的状态
   --- B)LED灯一个
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity led is
port(clk,reset,key:in std_logic;
     q:out std_logic);
end led;


architecture rtl of led is
signal clock1:std_logic;
signal clock2:std_logic;
signal count_key:integer range 0 to 2;
begin


process(reset,clk)
variable count1:integer range 0 to 200;
variable count2:integer range 0 to  200;
begin
 if reset='0' then
count1:=0;count2:=0;
elsif rising_edge(clk) then
if count1=200 then
count1:=0;clock1<=not clock1;
if count2=200   then
clock2<=not clock2;
count2:=0;
else count2:=count2+1;
end if;
else count1:=count1+1;
end if;
end if;


end process;


process(key,clock1,reset)


begin


if clock1='1' then
if reset='0' then count_key<=0;
elsif rising_edge(key) then
      if count_key=2 then
         count_key<=0;
      else count_key<=count_key+1;
   end if;
end if;
end if;
end process;


process(count_key,reset)
begin
if reset='0' then q<='0';
end if;
case count_key is
when 0=>q<=clock2;
when 1=>q<='1';
when 2=>q<='0';
when others=>end case;
end process;
end rtl;

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