原创 简易频率计

顶层文件

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY jypyj IS
 port
 (
  clk :  IN  STD_LOGIC;
  fun :  IN  STD_LOGIC;
  seg :  OUT  STD_LOGIC_VECTOR(6 downto 0);
  temp :  OUT  STD_LOGIC_VECTOR(3 downto 0)
 );
END jypyj;

ARCHITECTURE bdf_type OF jypyj IS

component fenpin
 PORT(clk : IN STD_LOGIC;
   clk1 : OUT STD_LOGIC;
   clk2 : OUT STD_LOGIC
 );
end component;

component kongzhi
 PORT(clk1 : IN STD_LOGIC;
   count : OUT STD_LOGIC_VECTOR(1 downto 0);
   temp : OUT STD_LOGIC_VECTOR(3 downto 0)
 );
end component;

component led
 PORT(data : IN STD_LOGIC_VECTOR(3 downto 0);
   seg : OUT STD_LOGIC_VECTOR(6 downto 0)
 );
end component;

component xianshi
 PORT(clk_mux4 : IN STD_LOGIC;
   count : IN STD_LOGIC_VECTOR(1 downto 0);
   dout1 : IN STD_LOGIC_VECTOR(3 downto 0);
   dout2 : IN STD_LOGIC_VECTOR(3 downto 0);
   dout3 : IN STD_LOGIC_VECTOR(3 downto 0);
   dout4 : IN STD_LOGIC_VECTOR(3 downto 0);
   led_data : OUT STD_LOGIC_VECTOR(3 downto 0)
 );
end component;

component ctr
 PORT(fun : IN STD_LOGIC;
   end_time : OUT STD_LOGIC;
   en_on : OUT STD_LOGIC;
   en_off : OUT STD_LOGIC
 );
end component;

component jishu
 PORT(clk2 : IN STD_LOGIC;
   begin_stop : IN STD_LOGIC;
   reset : IN STD_LOGIC;
   dout1 : OUT STD_LOGIC_VECTOR(3 downto 0);
   dout2 : OUT STD_LOGIC_VECTOR(3 downto 0);
   dout3 : OUT STD_LOGIC_VECTOR(3 downto 0);
   dout4 : OUT STD_LOGIC_VECTOR(3 downto 0)
 );
end component;

signal SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 downto 0);
signal SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(1 downto 0);
signal SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 downto 0);
signal SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 downto 0);
signal SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 downto 0);
signal SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 downto 0);
signal SYNTHESIZED_WIRE_8 :  STD_LOGIC;
signal SYNTHESIZED_WIRE_9 :  STD_LOGIC;
signal SYNTHESIZED_WIRE_10 :  STD_LOGIC;

BEGIN

b2v_inst : fenpin
PORT MAP(clk => clk,
   clk1 => SYNTHESIZED_WIRE_0,
   clk2 => SYNTHESIZED_WIRE_8);

b2v_inst2 : kongzhi
PORT MAP(clk1 => SYNTHESIZED_WIRE_0,
   count => SYNTHESIZED_WIRE_3,
   temp => temp);

b2v_inst3 : led
PORT MAP(data => SYNTHESIZED_WIRE_1,
   seg => seg);

b2v_inst4 : xianshi
PORT MAP(clk_mux4 => SYNTHESIZED_WIRE_2,
   count => SYNTHESIZED_WIRE_3,
   dout1 => SYNTHESIZED_WIRE_4,
   dout2 => SYNTHESIZED_WIRE_5,
   dout3 => SYNTHESIZED_WIRE_6,
   dout4 => SYNTHESIZED_WIRE_7,
   led_data => SYNTHESIZED_WIRE_1);

b2v_inst5 : ctr
PORT MAP(fun => fun,
   end_time => SYNTHESIZED_WIRE_9,
   en_on => SYNTHESIZED_WIRE_2,
   en_off => SYNTHESIZED_WIRE_10);

b2v_inst6 : jishu
PORT MAP(clk2 => SYNTHESIZED_WIRE_8,
   begin_stop => SYNTHESIZED_WIRE_9,
   reset => SYNTHESIZED_WIRE_10,
   dout1 => SYNTHESIZED_WIRE_4,
   dout2 => SYNTHESIZED_WIRE_5,
   dout3 => SYNTHESIZED_WIRE_6,
   dout4 => SYNTHESIZED_WIRE_7);

END;

分频程序

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
       Use ieee.std_logic_unsigned.all;
      
       Entity fenpin is
             Port(clk:in std_logic;----系统时钟为50KHZ
clk1:buffer std_logic;
clk2:out std_logic);
      end fenpin;
architecture rtl of fenpin is

begin
process(clk)
  variable a:std_logic_vector(5 downto 0);
  begin
   if rising_edge(clk) then
         a:=a+'1';
if a="110001" then   a:="000000";clk1<='1';
else clk1<='0';
end if;
end if;
end process;

process(clk1)
variable b: std_logic_vector(3 downto 0);
begin
if rising_edge(clk1) then
         b:=b+'1';
if b="1001" then   b:="0000";clk2<='1';
else clk2<='0';
end if;
end if;
end process;
end rtl;

控制程序

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
       Use ieee.std_logic_unsigned.all;
      
       Entity kongzhi is
             Port(
clk1:in std_logic;
count:out std_logic_vector(1 downto 0);
temp:out std_logic_vector(3 downto 0)
 );
        end kongzhi;
architecture rtl of  kongzhi is

begin

process( clk1 )
  variable abc: std_logic_vector(1 downto 0):="00";
  begin
  if rising_edge(clk1) then
if abc="11" then abc:="00";
else abc:=abc+'1';
end if;
end if;
case abc is
when "00"=>temp<="0001";
when "01"=>temp<="0010";
when "10"=>temp<="0100";
when "11"=>temp<="1000";
when others=>temp<="0000";
end case;
count<=abc;
end process;

end rtl;