原创 Wafer Top Electrostatics Induced Damage Mode at SEMI Wafer Fabrications

Figure1. the modes of wafer top electrostatics induced failures

Such wafer top electrostatics failure mode exists in many processes, including the vacuum processes of PECVD (PID, Plasma process Induced Damage), Dry-etcher (PID), Asher (PID) and atmosphere processes of HPW (Highly Purified Water) rinsing cleaning, Spin dryer after rining cleaning, scrubber cleaning with spinning, etc.

Figure2. a typical HPW rinsing cleaner with spinning

Eventually, the back-end manufacturing of semiconductors (Chip Assembly and Testing) also exist such wafer top electrostatics induced damage and the process is also the rinsing cleaning at wafer sawing process. However, due to the big differences of wafer interior circuits, the production yield failure problem caused by such wafer top electrostatics is much more sensitive and severer in wafer Fabs than chip assembly and testing production lines.

Figure3. PID problem in a dry etcher of wafer Fabs

The Wafer top electrostatics induced damage mode is also highly related with wafer internal circuit layout and process technology scaling levels. Among nowadays mainstream semiconductor products, more and more fall into the scope of 65nm technology process and below. Typically, the sensitivity level of such wafer top electrostatics induced failures at wafer fabs most goes to below 100 volts and even only several volts for the most advanced semiconductors.