标签: fab

半导体前端制造wafer fab中必须要做静电防护的一个重要光刻工具-photomask（reticles），否则静电导致的photomask的CD（Critical Dimension，）不良（对65nm制程技术及以下有位敏感）必然会导致半导体器件的光刻良率损失甚至于全部报废。 转载自微信公众号“ESDiS Release”。原文链接： https://mp.weixin.qq.com/s?__biz=MzkzMDU2MDkwNQ==&mid=2247483725&idx=1&sn=b99dfbc91d9e172b1c1125bd80771d63&chksm=c2792fabf50ea6bdea3c11752a06bc292c90345525f381578c6efc6d54d9376a91ff44158905#rd Keywords of Glossary Reticles, also called as photomask, it usually utilize quartz or glass as the substrate and coated with an opaque film (often chrome) of the designed pattern on it which is etched the design of the device being manufactured. SMIF pod, it provides reticles users with a standard mechanical interface (SMIF) to the safe handling, storage and transportations within fabs. EFM, it refers to electric field induced ion migrations (mainy for chrome ions coated on reticles). ESD, Electro-Static Discharge, it refers to the abrupt transfer of static charges under the influences of electric fields. The Electrostatics Susceptibility of Reticles Regarding the features of large amounts of diverse chrome patterns with micro spaces (presently most reticles of IC products fall below 1um range) on the insulating glass or quartz, reticles would exhibit very high susceptibilities to electrostatics, involving EFM and ESD events. Figure 1. the micro level isolated chromes patterns of SEMI reticles Regarding EFM problems of reticles, usually it occurs when reticles approaches higher electrostatic sources or reticles substrate was electrostatically charged up higher during handlings in fabs. EFM would induce reticles inspection failures of CD (critical dimension) variations. EFM impacts of reticles could be accumulated over a long time electrostatics exposures. Figure 2. CD failures of reticles caused by EFM events Regarding ESD problems of reticles, usually it occurs when reticles are exposed to very higher electrostatics than EFM events. ESD events of reticles (within reticles or between reticles and other items involved) often lead to chrome patterns with damages of mice bits or short bridges. Figure 3. reticles with ESD damages of mice bites type Figure 4. reticles with ESD damages of short bridges and / or melting Electrostatics Risks evaluation Method Wafer fabs could obtain the appropriate commercial E-reticles product to evaluate the electrostatics risks under control or out of control. This evaluation data could specifically help fabs to pin out the real electrostatics risks and take effective countermeasures for improvement. Fabs could also design and manufacture the E reticles by themselves. Figure 5. E reticles used to evaluate reticles electrostatics risks The Electrostatics Controls of Reticles in SEMI Wafer Fabs The electrostatics controls of recticles in wafer fabs involves storage, handlings in production automation equipment (mainly for lithography) and transportations. Storage: reticles shall be enclosed in the SMIF pods or boxes which could provide the complete electrostatics protections against EFM and ESD. Handlings within automation equipment: the enclosed electric field shielding approach cannot be feasible within automations, the environment of reticles moving must be controlled at low electrostatics level and AC fields especially near reticles needs also be controlled at low levels. Transportations: Due to many insulating materials used in fabs, reticles transportations shall be put into SMIF pods with fully electrostatics protections prior to transportations.

同文转自微信公众号“ESDiS Release”。每间wafer fab都存在的静电问题。 The electrostatics problems in the front-end manufacturing of semiconductors (ie. wafer fabrication) is quite different from those cases in back-end semiconductor manufacturing (ie. Chip assembly and testing), SMT and other common electronic manufacturing industries. Among the electrostatics problems, the electrostatics induced electrical failures of microelectronic devices is the typical representative case, ie. wafer top electrostatics damage mode. Figure1. the modes of wafer top electrostatics induced failures Such wafer top electrostatics failure mode exists in many processes, including the vacuum processes of PECVD (PID, Plasma process Induced Damage), Dry-etcher (PID), Asher (PID) and atmosphere processes of HPW (Highly Purified Water) rinsing cleaning, Spin dryer after rining cleaning, scrubber cleaning with spinning, etc. Figure2. a typical HPW rinsing cleaner with spinning Eventually, the back-end manufacturing of semiconductors (Chip Assembly and Testing) also exist such wafer top electrostatics induced damage and the process is also the rinsing cleaning at wafer sawing process. However, due to the big differences of wafer interior circuits, the production yield failure problem caused bysuch wafer top electrostatics is much more sensitive and severer in wafer Fabs than chip assembly and testing production lines. Figure3. PID problem in a dry etcher of wafer Fabs The Wafer top electrostatics induced damage mode is also highly related with wafer internal circuit layout and process technology scaling levels. Among nowadays mainstream semiconductor products, more and more fall into the scope of65nm technology process and below. Typically, the sensitivity level of such wafer top electrostatics induced failures at wafer fabs most goes to below 100 volts and even only several volts for the most advanced semiconductors.

1. 关键词： FPD：Flat Panel Display，平板显示，当今主要包括TFT-LCD、LTPS-AMOLED（刚性屏与柔性屏） TFT：Thin Film Transistor，薄膜晶体管，LCD与AMOLED FPD显示器的基本驱动元器件，当前FPD的TFT技术类型包括a-Si、LTPS、Oxide TFT Array Glass：TFT阵列玻璃，上面包括LCD产品显示的基本驱动电路元件，是LCD产品显示面板两块玻璃之一 CF Glass：Color Filter Glass，彩色滤光玻璃，是LCD产品显示面板的另一块玻璃 LCD：Liquid Crystal Display，液晶显示器 Mother glass：母板玻璃，FPD产品前段Fab与中段Cell的产品型态，一张mother glass上可以切出多块显示屏的面板（single panel） 2. FPD产品的全段制造过程 FPD产品的生产制造分为Front-end前段（TFT Array Fab， Color Filter Fab）、Middle-end中段（Cell成盒装配）与Back-end后段（Module装配）。其中以front-end Fab为FPD产品制造涉及的生产工艺技术最为核心（ 这也是后端模组工厂客户以及FPD终端客户很少有机会接触到的产线 ），同时也是静电影响FPD产品生产良率、产品可靠性最为主要的生产过程。 图1. FPD全段制造的前中后段 3. FPD产品Front-end Fab产线中的静电风险简览 FPD产品front-end Fab阶段，以TFT array Fab的生产过程中的静电导致的问题为主。 TFT Array Fab生产过程，就是在mother glass上通过与半导体wafer Fab类似的工艺技术制作出TFT器件为主的array线路的各膜层器件元件。而TFT的fab过程中TFT glass的各种产品型态就容易受到较强的静电作用，从而导致其中局部线路元件的电性损坏，参见前述的文章《概说静电对于微电子产业的影响》。 图2. 5层光罩BCE TFT Fab制程 而TFT array各膜层的大量生产工序涉及的工艺操作都会产生并会不断累积高静电，从而TFT array glass的静电损坏来自于这些高静电带电的生产工序。 图3. TFT Array Fab主要工序流程 TFT array Fab生产过程中的静电产生与累积 TFT array fab中大量生产工序包括低压真空环境下的沉积镀膜、刻蚀与常压环境下的涂覆、曝光、检测等。 以常压环境的生产设备exposure（曝光）为例，TFT array glass进入设备中，完成曝光过程，再送出设备的过程，就会在glass上累积大量的静电（ 尤其是使用多年的设备，玻璃带高静电显著更高 ）。而这种glass操作产生大量静电的过程，在其他设备上也是常见的。 图4. TFT Array Fab中真空吸附平台上顶起玻璃的过程产生大量静电 TFT array Fab产线中都有很多rolling transfer线体用于在不同工序间来穿传送array glass。而glass在roller上的传送过程就会不断在glass背面累积大量的静电。 图5. TFT array Fab rolling transfer导致玻璃上累积高静电 FPD产品以智能手机屏为例，一款6.5英寸的屏幕（分辨率1600*720），其TFT array glass上的显示区域的TFT就有3456000个之多，另外手机屏上有效显示区域之外的区域也含有大量包括TFT等元件构成的显示控制线路。 图6. 6.5英寸LCD手机屏幕 （源自OPPO A11S） 由此，一块手机屏幕TFT array glass的Fab生产过程都要经过数十道乃至上百道上述生产工序。以当前业内生产手机屏幕的6代线（玻璃尺寸1850*1500）为例每张mother glass上有200多块6.5英寸的手机屏，每块手机屏上包含300多万颗TFT等元件。所以， 要将TFT array Fab工厂产线的静电不良率控制到很低的目标，对于每一个Array Fab工厂来说，其技术难度与生产工艺控制挑战性都会是一项艰巨而庞大的工程。

It had been a while since I visited India for biz and my recent trip to Bangalore for the Indian Electronics Semiconductor Association (IESA) Vision Summit 2015 early this month was an eye opener on the vast potential the country holds as an economic power. All of us are aware of the euphoria building up with the new Prime Minister and his forward-looking pro-business policies. Countries including US, Japan, Australia and others have been pledging very high amount of business interests into India. The Make in India mantra to transform the country from a consumer state to a manufacturing one has been gaining a huge amount of momentum. A big focus here is the resurfacing of semiconductor wafer fab manufacturing initiative and what better opportunity than this could be for the mature semiconductor manufacturing industry ecosystem in Singapore to take advantage of and look for significantly large business opportunities. A significantly high profile event, the Vision Summit attracted 600+ delegates. I had the opportunity to share the stage with some eminent industry leaders who shared their insights on this high value manufacturing. The panel discussion, "Semiconductor Fab – The Opportunity, Challenges Accelerators" was quite lively and interesting. The place was abuzz with activities and I list below a few of my takeaways on the Indian semiconductor happenings. Focus on Semiconductor Fabs in India Long been a missing key entity in the Indian semiconductor eco-system, this has got a renewed focus from the Government of India, especially courtesy the alarmingly increasing trade deficit gap for electronic products and components in the country. Most of the demand from the huge electronics growth – fuelled by increasing purchasing power of a large domestic market—is presently being met through imports. With the present domestic electronics production and services still lagging behind and the demand projected to rise, this gap is expected to widen further. In fact, India’s electronic goods and component import bill is expected to far exceed its oil import bill at this rate. The government is paying attention and fast tracking these initiatives/activities to avoid a future crisis due to this deficit gap. Last year, the Indian government gave the go-ahead for 2 semiconductor consortia to set up fabs in the country. One consortium includes Jaiprakash Associates, Tower Semiconductor and IBM and the other includes HSMC Technologies, Silterra and STMicroelectronics. The sites for the two proposed fabs (one from each consortium) have already been identified – the former in the state of Chattisgarh and the latter in Gujarat. The setting up of the fabs will open up huge opportunities for ancillary industries too – besides the fab infrastructure, equipment and material vendors etc. Expect to have the ecosystem quickly developing around these fabs once the ground-breaking starts. Singapore with its mature semiconductor manufacturing eco-system has much to offer here. Companies in   Singapore have evinced keen interest and are awaiting some clear signals on the fabs’ start-up timeline and status. States wooing businesses and investments A pleasant surprise for me personally was to see the "men in power" aka state government officials actively wooing for businesses and investments in their states – a 180-degree turnaround from the earlier days! The "Make in India" focus from the Indian government includes several growth and industry conducive policies and incentives as it aims to transform India from a consumption driven market to one with manufacturing capability. Several state governments were present and actively pitching for their states. MoUs and White Paper A few MoUs were signed signalling collaboration between industry- academia as well as across industry associations between countries. IESA and SSIA (Singapore Semiconductor Industry Association) signed a MoU agreeing to establish and develop trade and technical cooperation links between the electronics and semiconductor manufacturers of both countries in general and their respective members in particular. IESA and SSIA also jointly released a White Paper on India Singapore ESDM (Electronics Systems Design and Manufacturing) industry collaboration opportunities—the latter is something that I had also worked on, on behalf of SSIA. Strong presence of Small and Micro-small business entities This is a rapidly increasing sector and denotes a strong entrepreneur mind-set. This includes people previously having worked in MNCs and starting up something in a niche, returning Non-resident Indians eager to leverage on the Make in India focus, traditional family run businesses entering the services sector in this space and a sizeable number of experience rich freelance consultants. The government has also come up with initiatives to address this important and, if I may add, "neglected but vital" segment. Keynotes, Panel discussions, Press briefings Quite a few insightful and passionate keynotes. Speakers included Dr K. Radhakrishnan, Former Chairman, Indian Space Research Organisation, Mr Gururaj Deshpande/Sparta Group, Tejas Networks and top leaders from companies like Seagate, MediaTek, Imagination Technologies, Rambus, Intel and others as well as speakers for the different state governments (Chief Minister, Secretary to State etc.). There were panel discussions on "Transforming India – movers shakers", "Fuelling the wheels of change – the essentials", "States – The fulcrum of ESDM Policy implementation", "Realising smart cities with IoT", "Semiconductor Fab – The Opportunity, Challenges Accelerators" and "Building the ESDM start-up ecosystem". The event elicited significant press coverage. Being a part of some of the press briefings, it was heartening to note the interest of the media in this space and especially on the increasing collaboration across countries as a vital path to fast track the growth of the local ESDM ecosystem.    

Make your own ICs using, well, much less than a big fab. At the Boston ESC last October I met Chris Gammell, an interesting young feller who runs, among other things, The Amp Hour , a blog site that has always-interesting content. His latest entry sports referred me to a video from noted life hacker Jeri Ellsworth which shows how one can build a personal chip using not much more than a kiln and a lot of clever tricks. It's an 8 minute flick, far longer than the sort I usually watch. Who has the time to view all of the videos passed around on the Internet? I sure don't, and only rarely visit video sites, and then only after a recommendation from a trusted source. But this one is quite breathtaking. Turns out you don't need a $5 billion fab to build your own IC. Intel watch out! Instead she uses, for instance, a CPU fan. She tapes the chip onto the hub of the fan and spins off the phosphorosilica. Simple, effective, and insanely cool. Of course, the geometry is somewhat more coarse than 45 nanometers (nm). At the end of the video she shows a five transistor chip that's a couple of inches long. And the next video on her site is a demo of the part. But it works. And that's astonishing in this day when we assume chips come from Digikey, and are manufactured somewhere on the planet in fabulously complex fabs. I sometimes wonder if electronics has become so complex that it has lost its appeal to youngsters. In my youth we built ham radios and other gear using discrete transistors, vacuum tubes, and the smallest of small scale ICs. Today one must wrestle with surface mount technology (SMT) and datasheets a thousand pages long. But this video shows that being smart and inventive, and, alas, being young and not bound by convention, can keep the cool in this cool field. The video is also one of the most dramatic uses of PowerPoint I have seen to date. Cliff Stohl gave a couple of ESC keynotes years ago using notes scribbled on his arm. Jeri's technique is a bit more sophisticated, but is eminently clear, much more so than so many bulleted lectures I've attended. Recommended. Especially for those who get jaded by the fearsome complexity of modern electronics.