原创 用可综合的Verilog模块设计复杂的多输出状态机

module  fsm (Clock, Reset, A,  K2, K1,state);
input Clock, Reset, A;
output K2, K1;
output [1:0] state;
reg K2, K1;
reg [1:0] state, nextstate ;

parameter   
Idle     =  2'b00,  
Start    =  2'b01,  
Stop     =  2'b10, 
Clear    =  2'b11;
//-------- 每一个时钟沿产生一次可能的状态变化----------- 
always @(posedge Clock)
  if (!Reset)
        state <= Idle; 
   else
        state <= nextstate; 
//-------------------------------------------------------
//------ 产生下一状态的组合逻辑 -------------------------      
always @(state or A)
     case (state)
        Idle:  if (A)    
                 nextstate = Start;      
                else  nextstate = Idle;
       Start:  if (!A)  nextstate = Stop;
                  else   nextstate = Start;
       Stop:  if (A)  nextstate = Clear;
                else  nextstate = Stop;
       Clear:  if (!A)   nextstate = Idle;
                else   nextstate = Clear;
      default:  nextstate =2'bxx;
  endcase
//-------------------------------------------------------
//---- 产生输出K1的组合逻辑 --------------
always @(state or Reset or A) 
  if (!Reset) K1=0;
    else
       if (state == Clear && !A)  //从Clear转向 Idle
               K1=1;
        else   K1= 0;
        
//--- 产生输出K2的组合逻辑 ---------------
always @(state or Reset or A ) 
   if (!Reset) K2 = 0;
  else
      if (state == Stop && A)  // 从Stop转向 Clear
               K2 = 1;
	        else K2 = 0;
//------------------------------------------
endmodule

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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "06/09/2024 19:25:15"
                                                                                
// Verilog Test Bench template for design : fsm
// 
// Simulation tool : ModelSim-Altera (Verilog)
// 

`timescale 1ns/1ns
module t;
   reg a;
   reg clock,rst;
   wire k2,k1;
	wire [1:0] state;
initial              // initial常用于仿真时信号的给出。
     begin 
       a=0;
       rst = 1;       //给复位信号变量赋初始值
       clock = 0;      //给时钟变量赋初始值
       #22 rst = 0;    //使复位信号有效
       #133 rst = 1;   //经过一个多周期后使复位信号无效
     end

     always #50 clock = ~clock; //产生周期性的时钟

     always @ (posedge clock)   //在每次时钟正跳变沿时刻产生不同的a 
        begin   
             #30 a = {$random}%2;   // 每次a是 0还是1是随机的。
             #(3*50+12);  // a 的值维持一段时间
        end
    initial
      begin   #100000   $stop;  end   //系统任务，暂停仿真以便观察仿真波形。

//----------- 调用被测试模块t.m ----------
 fsm  m(.Clock(clock), .Reset(rst),.A(a),.K2(k2),.K1(k1),.state(state));    
    
endmodule   

仿真波形：

从图中可以看出;state=3,a=0时，K1拉高。
从上图可以看到;
state=2,a拉高，K2拉高。