tags: astedit astro clock tree astro sync port astro tlu astro create netl astsetdontuse astro macro placement flow astro astchangenetlist script astro change netlist postplace disable clock gating check astro default clock astro fix timing after placement astro generating clock tree astro make macro cell in astro astro leq tdf files pad placement in astro how to remove drc violation in astro
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1.powerful PhySiSys" technology and the new Milkyway-DUO" (Dynamic Unified Optimization) architecture.
2. including timing, signal integrity, crosstalk, power, die size, routability and manufacturability.
3.design closure
4.synthesis netlist optimization
5.physically accurate silicon models
6.Milkyway Duo is the run-time database.
7.Astro & Apollo: most of the key algorithms have been rewritten including logic optimization, timing analysis, placement, and clock tree synthesis.
Other features have been added such as hierarchy preservation and overlap removal.
8.parasitic extraction,
9.dump out the HSPICE information
10.CG (netlist):CG: Common Graph: common graph is a bare bones netlist.
11.PDS: Placement Driven Synthesis
12.Call Back:
13.Overlap Removal:It allows functions like PDS and CTS/CTO to instantaneously determine the effects of a sized or added cell and then remove the change if it degrades performance.
14.Apollo/Saturn.
15.Some simple methods of optimization are not used by Saturn, such as gate duplication, net splitting, and inverter insertion.
16.Scan optimization includes the ability to maintain the original module ports
in the hierarchical netlist.
17.Congestion based coupling estimation for preroute extraction.
18.manufacturability issues (such as antenna checking and fixing).
19.***************************
In addition to continuing to support Synopsys .lib format, with Astro, Synopsys
adds translation of Synopsys STAMP models. In addition ALF models are also
supported. All of these are translated into Synopsys CLF format and/or Astro
TIM model format.
*****************************
Cadence: ILM model: Interface Logical Modeling
20.Create Capacitance Model: TLU Cap Models
StarRCXT ITF file,
21.ApolloToAstroCmdConversion.Map
ap2ast
22.In Apollo, timing constraints are stored in the cell database in a TDF table.
Astro will only read SDC syntax for timing constraints.
23.CEL and TIM views in Apollo,
24.Logically Equivalent Cell (LEQ) Information
25.Cell Delay Model - TLU
Wire Delay Model - AWE
26.Loading Power Supply Information
27.If loaded, crosstalk analysis will use power supply information loaded into the tool.
******************************
If not provided, crosstalk analysis will still work since it can be based on
a voltage value independent of supply value. For multiple voltage
designs, users are recommended to load the power supply information
in order to get accurate analysis since noise metrics are percentages of
the power supply. For single voltage supply designs the result will be the
same with or without the supply loaded.
*******************************
28.HCG (Hierarchical Common Graph):astInitHierPreservation
modules that must be preserved:astMarkHierAsPreserved
29. CLF
30.Read in verilog description to create .NETL view.
Expand the netlist (.NETL view) to create a .EXP view.
Create a cell view .CEL and bind netlist view .EXP.
Add Cells not in the netlist such as pwr/gnd pads.
Set power/ground ports using Preroute > Connect Ports to P/G
Initialize hierarchy preservation information using
31. expanded netlist view (.EXP),
If you want to dump a hierarchical netlist using astDumpHierVerilog, then at a
minimum, astInitHierPreservation, should be done.
32.Delete hicon ports using astRepairHierPreservation since PrimeTime can
not find these nets.
33.Backslash before hierarchical name.
Strip BackSlash
This option will strip the backslash before the hierarchy separator. In almost all cases it should be left at the default value of ON.
34.Dont use EXP view to do astInitHierPreservation, use the CEL and NETL
views.
35.Remember to set correct busStyle for the library. Users should see a
warning message on bus Style when generating hierVerilog.
36.Use astCheckHierPresConsistency. This command checks if hierarchical
information (HCG) in the cell is consistent with the flat CG. It works on a current open cell and loads CG if it is not already loaded. It generates CGHIER errors, if there is any difference in the HCG and CG data.
37.Astro can take both TCL based and non TCL based SDC constraints,
38.SDC constraints that would be generated by the write_sdc function should be avoided since they are expanded. It is better to load SDC with wildcards into Astro than an expanded SDC.
39.Often constraints used for final timing verification, or for initial synthesis, are not appropriate at all stages of physical optimization. For example, it is not correct to set propagated clocks or allow data/clock mixed paths prior to building the clock tree. Other examples include the use of case analysis.
40.Either astInitHierPreservation or cmCreateHierPorts should be run prior to loading SDC file in order that SDC constraints to hierarchical ports (which disappear during flattening) can be properly considered.
********************************
41.ExamineSDC:
set_propagated_clock
set_case_analysis
********************************
42.
TDF: Timing Setup Tabs,
43.TDF pin/pad commands will be used to control the physical location of pins and pads only. There are no timing related TDF commands in Astro.
44.SDC information is not backward compatible
45.OV, PPO
46.Timing > Write Design Constraints (astWriteDC)
Input is : SDC
47.LEQ
48.LPF:
49.TLUPlus uses Star-RCXT model generation to create TLU capacitance tables.
50.Net Delay Model
It is recommended to set Elmore prior to routing and AWE after routing.
51.There are two ways to buffer high fanout nets in Astro; during PrePlacement Optimization and using Astro CTS.
52.Typically, scan enables should be buffered by Astro CTS since the loads
will be declared as scan clock in the port types file. To keep PrePlacement
Optimization from buffering these nets simply declare the scan enable as a clock.
53.Astro will automatically handle high fanout nets during the flow; therefore, for most nets, there is no need to set a transition or cap default.
54.There is data and clock mixing causing a high fanout clock node in a critical path. This path will not be fixed by preplace optimization because the net is partially clock.
55.Setting Net Transition Defaults for Non-Clock Nets
56.Loading ataSetNetCapTransAndDelay will create a .TIM view to store the information. You should immediately save the .TIM after loading the step. The best way is to use Cell > Save All Open Cells! (geSaveAllOpenCells). In a replay script, you can avoid the query boxes that pop up for this command by doing the
following:
setDisplayMode "QueryBoxes" #f
geSaveAllOpenCells
This is especially helpful when running in nullDisplay mode.
57. COmbinational feedback loop
58.is timing path from latch to latch and both driven by same clock with
same path,
59.reports latch self loops, a situation
where a latch output may drive its input through combination logic.
60.
Currently, the design needs to be placed for astCheckDesign to work. A simple
way to do this is to use astFastPlace (geGetEditCell). Note that this
placement is not based on congestion or timing or any other normal placement
parameters. It simply places cells in legal locations.
61.The ataCompare command will provide all the information needed to back
annotate to Synopsys DC and PrimeTime.
62.The zero interconnect timing report after preplacement optimization
provides a good indicator of final timing result.
63.Zero interconnect can hide problems with SDC affecting optimization of
certain parts of a design. It is recommended that the user should evaluate
timing closely after clocks are inserted and post-place optimization is
completed and prior to proceeding to routing.
64.To run zero interconnect timing in PrimeTime, simply do not provide any
wireload models in the .lib files read by PrimeTime. The .lib files dumped by
Astro will not contain wire load models.
65.ataCompare:
This will also allow current Astro timing constraints and Synopsys
CLF information to be translated to Synopsys format so that
PrimeTime or DC can use the same constraints and timing
information Astro uses.
ataCompare is meant to aid debugging in the case that the user does not have
access to the original .lib files. It is not recommended for production flow
because only limited QA is done. Synopsys recommends always using original
.lib files when comparing Astro to PrimeTime.
66.It is design dependent. However, in general we would like to see pre-route RC results in reasonable but little pessimistic range than post-route in order to predict design closure quality and achieve consistent design convergence.
67.To make preroute a little more pessimistic use the settings below
68.Adjusting Preroute Pessimism/Optimism of Caps
69.Guideline would be to make preroute 3-5% pessimistic at most, and then use
route optimizations to close remaining nets. Settings to adjust preroute
capacitance/resistance in Astro:
axSetRealParam "ek" "capMultiplier" 1.05
axSetRealParam "ek" "resMultiplier" 1.05
70.Checking TLU Cap Model Parameters
71.Geometry Scaling Factor:
72.Max Distance to Extract Lateral Capacitance:
Also in technology file there are Cap Multiplier (Individual) settings for
each layer. Apollo and Astro both do take them
73.TLUPlus models are generated using grdgenxo; to create them you need a
description of the process technology in Interconnect Technology Format (ITF),
which may be supplied by the foundry or created by the user. A map file will also be needed, to map the process layers to the Milkyway library technology file.
74,Interconnect Technology Format (ITF)
75.Soft blockages prevent cell instances from being placed inside except for cell instances that are either fixed or softfixed.
76.(hard or soft) placement blockage.
77.A soft-fixed cell instance cannot legally stay within hard placement blockages.
78.the placer engine sees soft as hard, but optimization commands see soft as non-existent.
79.Assign a level shifter cell from one voltage group to another using
astSetLevelShifter.
80.Connections between scan outputs and scan inputs in a scan chain may not be
optimal for routing after placement. However, now, scan clocks often run at
higher frequencies so that the tool needs to optimize them as well. In addition
hold times need to be fixed after scan flipflops are placed and the chain
connections are optimized.
81.The preferred method to reconnect and optimize is to do it after placement and clocks are inserted and prior to post placement optimization.
This would allow
postplacement optimization to optimize the chain for timing as needed.
If you do not want postplacement optimization to work on the re-connected
chain, then wait until after postplacement optimization to reconnect the chain.
82.dbMarkScanPortPairs and dbDumpScanPortPairs should be used if a
cell has multiple scan input and output ports.
83.This function performs a quick placement, high-fanout collapse, high-fanout net synthesis, gate-sizing, moving-cell, buffer/inverter bypassing, buffer insertion, inverter insertion, gate-duplication, net-splitting, area-recovery, and remapping.
The netlist changes will apply cell movement so ECO-place will be invoked. Overlap Removal (OV) is not invoked during prePlace optimization.
84.Therefore, it is recommended to rebuffer these in Astro based on the actual
physical placement. Setting the value lower tends not to improve optimizations much, but can increase the runtime since Astro must rebuffer these nets. Setting the value to 1 will remove all buffers from the design.
85.In benchmarks it has been found that when synthesis inserts buffers for fanouts greater than 10 it can interfere with Astro optimizations and increase congestion.
86.Area Recovery will eliminate buffers and downsize cells. By default the
utilization at which this occurs is 50% - as specified on the timing setup panel. Use the timing setup panel to lower this threshold if you want more recovery to occur.
87.Ideal Optimization will try to optimize the design with zero interconnect. On large designs it may be better to turn this off in order to save run-time.
88.Enforce Full Place makes the tool do a full quick placement before trying to fix high fanout nets. If not selected it will just run ECO placement.
*************************************
89.Astro, our strategy has been, at an earlier stage, we need to do more massive changes such a HFN opt before the detailed placement begins.
*************************************
90.Release Note: Max Transition and Max Capacitance are no longer optimized by
preplacement optimization nor placement with ipo. It is intended that the first
time transition and capacitance constraints are fixed is during postplacement
phase 1 optimization.
91.If the number is very negative, the user should look at the critical path with zero interconnect timing. The only acceptable source for a large negative number is if data and clock mix.
If data/clock mixing is the cause of the
high slack, turn off mixed edges during timing analysis and redo zero
interconnect timing after preplace optimization.
92.quick Boolean matching
structural-based matching
93.max transition and max capacitance are concurrently optimized
during postplacement and postrouting optimizations.
94.pdsHFNOptimization can be used to buffer non clock nets. This is actually the function built into the HFN fixing contained in preplace optimization. It can be run stand alone after a placement exists. Some users may find it more convenient to buffer large high fanout nets, like resets or enables, using this function after real placement is finished instead of during preplacement optimization. ataSetNetCapTransAndDelayTime should be set on the net to specify a realistic capacitance, delay, and transition for the net and to prevent HF optimization during preplacement optimization.
95.How can I find all High Fanout Nets in a design? Use astDumpHFN:
Syntax: astDumpHFN n
This will dump out nets with n or more pins on it.
96.Useful skew is a method of intentionally skewing a clock in order to improve the timing on a circuit.
97.There are two basic flows given in the Astro Primer: CTS with Useful Skew, and Useful Skew Budgeting.
Useful Skew Budgeting normally be done at this stage of the flow - after preplacement and prior to placement.
98.The first uses
optimizes the design completely using the useful skew budget and then
recalculates useful skew prior to running CTS, and the second runs CTS based
on the original budget and then finishes the optimization. It is recommended to
use the first flow in most cases - since it will account for errors in the original budgeting.
99.postplace optimization phase 1
postplace optimization phase 2
100.The Constraint File on this form refers to a file that contains user-defined cell clusters that the placer should attempt to place together. This allows the user to specify master and instance padding, net weights, and cell clusters.
101.Timing-driven (including IPO)
Astro Place provides a smooth trade-off from 1 to 10 with 1 having more routability, and 10 having more emphasis on timing.
102.Incremental Place
This is the same function as found in Astros ECO Placer.
103.Macro and I/O Net Weighting
Macro nets are defined as nets connected to any macro pins.
104.Search and Refine capability.
105.User Place uses Overlap Removal (OV) package to incrementally remove
overlap.
106.Dump Time Borrow Script: This is primarily for back annotation purposes
(mainly to Synopsys PrimeTime). The script can be used to feed-back the
amount of borrowing Astro is using for latch based designs. Synopsys has found that you must use aggressive borrowing in order to optimize latch based designs. The borrowing script provides a way to minimize any correlation discrepancy.
107.astEdit can be used on designs after placement, after global route, or
after routing.
108.astChangeNetlist:
Force Change: This will allow you to change the netlist no matter what. For example, if the net is dont touch, clock net, etc. Therefore, the user must suffer the consequences if they try something wrong.
109. astEdit & astChangeNetlist
110.Since this is done in the middle of
placement, the timing result will not take into account all of the placement
moves associated with optimization -- this is the reason POST can be worse
than IN (if there were placement moves due to sizing, buffers, etc. that have
not been accounted for in the IN place number).
111.Timing/Library Debug Manager
The purpose is to provide some automation to verifying the timing analysis results vs. actual circuit simulation. In addition, the timing models can be reverified against the sub circuit information.
112.slew derate factor, etc.
113.The data book will quote three values of VDD, e.g.,
1.62, 1.80, 1.98
worst-case VDD = min
best-case VDD = max
typical-case VDD
The GUI form has a box where the user can type the value of VDD. Suppose that
the user has picked the condition to be the worst case. The user should type the worst-case VDD---
114.SPELLING OF VDD, VSS
Suppose that the vendor has spelled VDD as $VDD.
sed s/\$VDD/VDD/g subckt.sp > temp.sp
mv temp.sp subckt.sp
Suppose that the vendor has spelled VSS as $VSS.
sed s/\$VSS/VSS/g subckt.sp > temp.sp
mv temp.sp subckt.sp
115.DETERMINING THE PROCESS TAG
.LIB MODELS SlowSlow
The third phrase is the process tag---SlowSlow in the example above.
116.Stage Delay Checker:
A stage comprises a (signal) net, the driver of the net and the load(s) of the net. A stage is uniquely identified by the net name.
117.Note that the directory demTemp is temporary. If the user closes the Debugger Manager window, the directory will be removed automatically.
118.Topology Based Optimizations
Topology-based optimization is used throughout the Astro design closure flow.
119.placement and routing blockages.
120.Topology based fixing can be run at the placement stage, based on a quick global route, in order to correctly predict this situation and place the buffer in the optimum location.
121.Post-Placement Optimization Phase 1:]
This is the step where we take advantage of topology based optimizations, as
discussed above, prior to global routing or real routing.
Typically, it should only be run once. Depending on if postplace phase 2 is run before or after CTS, phase 1 will be either run before CTS or before initial phase 2 optimization (if phase 2 is done prior to CTS). In addition, it is recommended to redo high fanout net fixing that may have been done previously.
122.(phase 1)
Redo HFN Synthesis
At this stage we can base the high fanout clustering on the final placement. This tends to relieve congestion in the design. Previously, the purpose of high fanout optimization was to aid optimizations and during preplacement the clustering is based on a fast placement which is enough for that purpose. This step will do high fanout net collapse and then redo high fanout net fixing.
123. Fix Max Length
On some designs it helps to place buffers/inverters at specified lengths prior to doing detailed optimization. Typically these are large designs or designs with a lot of macro blockages.
124. Phase I:
setup time is not considered. Postplace phase 2 (astPostPS) should be used to
close the timing by doing detailed optimizations. The reason the two are not on
one form is allow the user more control. Postplace phase 1 (astPostPS1) is
typically done once to get the buffers inserted based on the topology. Phase 2
can be done as many times as desired, for example, prior to and after
propagating clocks.
125.******************************
PostPS I can only be done oce,
PostPS II can be done many times..
**********************************
126.Clocks must be inserted after placement. The overlap removal engine minimizes cell disturbances during CTS and CTO; therefore, when inserting clocks after placement, the timing result does not change much. Likewise because of overlap removal, postplace opt does not disturb the CTS result significantly. Also CTO can be run after postplace opt.
127.****
In patch 2 of Astro In-place CTS (concurrent CTS) has been removed
because of difficulties of getting the function to work dependably and
non-proven results. Users should build clocks after placement and
before postplace optimizations and then run clock tree optimizations
after postplace optimizations.
*************************************************************
128.Flow: PostPS I -> CTS -> PostPS II -> CTO ( For Patch 2)
*************************************************************
129.Clock Tree Synthesis (CTS) using global skew is the traditional method of
inserting clocks where CTS tries to make all the clock arrival times the same.
Typically designers looked for global skews that were 200-300 ps. With higher
clock frequencies the requirement for lower skew is needed since the clock
period is less. For example, 200ps skew for a 500MHz clock (2ns period)
represents 10% of the clock cycle. Often it is difficult to reduce the global skew further on a design; however, if local skew is used, then the tool only tries to reduce the skew on logically related flip-flops while ignoring the skew between non related flip-flops. This technique can reduce the skew on related flip-flops lower than the global skew of the design. In addition, if the global skew is too small, then there can be power problems due to the simultaneous switching of all flip-flops in the design at nearly the same time.
130. Global CTS & Local CTS....
131.**********Flow
The basic idea in this flow is to:
PreplaceOpt --> gives better netlist to placer
Placement with In-Place Optimization --> minimize congestion and timing
PostPlace Opt Phase 1 --> redo HFN fixing and use topology based design
rule fixing for transition, cap, length, and crosstalk
Build the clocks using global skew
Local Skew can increase the runtime of initial CTS
Optimize the design using PostPlace Opt Phase 2
Can propagate the clocks at this time if desired
Optimize the clock tree using Global or Local Skew
Re-optimize using PostPlace Opt Phase 2 with clock propagation (if
desired)
**************************
132.Post-Placement Clock Flow - Useful Skew Flow:
Propagate Clocks via SDC file
133.At this time it is not recommended to use Clock Tree Optimizations
with useful skew. In the future this may be a valid addition to the
above flow.
134.Currently the best way to control the amount of useful skew is to adjust the clock period.
135.Astro CTS can be used on gated and non gated trees by selecting the Gated Clock Tree button near the top of form.
136.To ensure certain buffers are not used during embedded CTO, please set
astDontUse property on the buffer - CTO will take any LEQ buffer set
by astSetClockCell (or in library is astSetClockCell is not specified).
Often, strong buffers create electromigration problems.
137.The clocks are considered in the order given on the astClockOptions form. It is recommended to put the most critical clock last in order to get best synthesis results.
138.In order to handle gated clock tree, we developed GCTS.
139.Starting in patch 3, CTA (clock tree analyzer) is able to search the optimal parameters for CTS. If you want to set parameters yourself (like previous releases), please turn OFF CTA, using:
axSetIntParam "acts" "CTA" 0
140.Basically astCTS will convert transition, fanout, and
cap to a capacitance value and then selects the smallest one.
141.Sometimes you may want to fix buffers/inverts after CTS to prevent them from moving in the future. Also, sometimes you want to CTS not to move sinks during/after CTS. Normally both of these are not necessary.
142.CTS produces a file of nets (net.acts) it creates. Prior to patch 1,
customers utilized this file to determine which nets are part of the clock
network. However, this file may be incomplete. If you run astCTS more
than once, you should rename the file before subsequent runs. Also, CTO
can delete/add nets, so that the nets contained in net.acts is no longer
valid. ataDumpClockNets is the safest way to ensure you have dumped
all clock nets.
143.Block vs. Top on the astCTS form
Block should be used on designs consisting of mostly standard cells. On the
following design types,top should be used:
chip level designs
big designs (e.g. size > 1mm^2)
macros are placed inside the design.
Qespecially if standard cells are placed around the macros
When top is selected, some clusters are identified based on their locations. Each cluster is driven by a sub-tree. The main purpose of this option is try to put fanout pins to a same branch if they are in the closed area.
******************************************
144.Clocks with Logic Overlay:
As a conclusion, we recommend to customers to synthesize two clocks at the
same time if they have logic overlap.
******************************************
145.dummy load insertion,
146.Embedded CTO
Embedded CTO is the built-in CTO capability inside CTS. It includes buffer
resizing, dummy load insertion, level adjustment, etc. The difference of
embedded CTO to post-route (or standalone) CTO is that the CTS engine is able
to dynamically refine its clock tree structure within the process of generating
clock tree, while post-route CTO focuses on further skew refinement after most
of the layout implementation (especially clock tree routing) is complete.
147.During CTS the buffers are controlled by the selection on the clock options form. During CTO the tool will use all LEQ buffers defined in the library or from astSetClockCell (if set). To keep from using some buffers, the user can use astSetDontUse. Note that astSetClockCell prevents other Astro Optimizations
from using the specified buffers/inverters for normal optimizations, so users
must be careful in this area.
148.To control which delay cells astSetDelayCell can be used. The specified delay cells will not be used by normal Astro optimizations except hold time fixing. Alternatively, the user can use separate functions specifically for Buffer Sizing and Dummy Load Insertion which provide greater control on the form for buffers, delay cells, and nets used.
149.AstroCTS:]
Sync Pins & Ignore Pins (??????????))
150.Buffering Non Clock Nets using CTS:
(1) Define a clock using tcl - create_clock;
(2) To set all inputs of a net to be synchronous,axSetIntParam
set_default_trigger_edge
(3) set all back;
*******************************************
151.Buffering Non Clock Nets using CTS: (Three Method.)
(1) Instead of setting the trigger edge parameter,(above)
(2) dbDefineSyncPin statements can be created for each sink on the desired net
(3) pdsHFNOptimization can also be used as described at the end of the
preplacement optimization chapter.
*******************************************
152.Basic CTS is the Astro equivalent of Apollos MCTS (multi-level CTS). It allows the user to provide a configuration file that completely specifies a non-gated clock tree structure and Astro will build it optimally.
153.Synopsys recommends customers build specific dummy load cells instead of
using generic buffers. Dummy load cells should only have input pin capacitance
and no logic function so that they have the smallest possible cell size to minimize the effect of additions on the layout utilization and congestion.
154.Incremental CTS:
A design may have some ECO changes (such as deletion of FFs, addition of FFs
and relocation of FFs). If these ECO changes are made after routing, we
recommend you use ECO CTS instead of CTO. Since CTO may break a lot of
routed wires, change a lot of cells locations and even change the netlist. The ECO CTS will consider routing costs while synthesizing and optimizing the clock tree.
155.One method is to optimize the design at postplacement is to run postplacement opt several times:
156.astPowerRecovery is used to do this either at the postplace optimization stage (after postplace phase 2) or after detail routing. If done after detail routing footprint matching can be done in order to minimize the extent of the design changes.
157.Effects of SDC on Timing Analysis and Optimization:
One technique to help check if there is a problem with max transition and max
capacitance constraints is to examine various timing reports:
(1) generate timing report with normal settings - ensure default clock is enabled on the timing setup form
(2) remove all case analysis statements and generate timing report;
(3) remove disable timing statements from the SDC and generate timing report
If the number of max transition or max capacitance constraints changes, the
design should be optimized to fix the problems. If setup and hold constraints
change, then at a minimum optimize only transition and capacitance. If setup and hold are the same as the normal operating conditions, then it does not hurt to optimize setup and hold, as well as transition and capacitance, at the same time.
158.Astro is designed to accurately predict the routing capacitance. Users should find that the Astro result is slightly pessimistic and will improve after routing. It is not expected that any significant increase in slack will occur between placed timing results and routed timing results.
159.Similar to Apollo, it is recommended that critical clocks in Astro be routed before other signals so that they will have the most direct routing. The easiest way to do this is to use Route > Route Net Group and select All Clock Nets on the form.
160.By default Astro will typically route more on the upper layers. If you want to influence this, i.e. push routes more toward top or more toward the bottom,
adjust routing cost...
161.The best routability will be achieved by using the defaults. Adjusting the
costs to use more upper layers (in order to utilize layers with more
desirable properties), for example, may make some designs unroutable.
It is recommended to only adjust the parameters after you have gotten a
trial pass to route, or almost route, clean.
162.The parameter (axSetIntParam "route" "layerExtraCostByRC" 2) used to be recommended, but it was found that this only works on designs that use a process with very high-resistance vias and with some customers with very different pitch/width/RC for different layers. In many cases it would make designs unroutable; therefore, it is no longer recommended.
163.To see all available parameters use: axPrintParams all . To see only the route ones use axPrintParams route . Note that there are global route, trackassign,
164. Route:
during global route, track assign, and detail route.
165.in-route BI/GS
166.The recommend flow to fix crosstalk is to set prevention during global route and track assign. Then achieve zero DRC violations after Search and Repair. Run axgAdvRouteOpt (discussed later) without crosstalk to optimize timing - if significant timing improvement is necessary. Then run crosstalk analysis (xtXTalkAnalysis) followed by axgAdvRouteOpt with crosstalk to optimize timing and crosstalk.
167.Release Note: It is not recommended to correct crosstalk during Detail Routing and Search & Repair any longer since it does not run the timer and the crosstalk evaluation is not accurate. See Chapter13 for more details.
168.Global Route Optimization (astPostGR):
This function may not always improve timing and should not be the standard
flow, but can help on some designs.
169.Post Route CTO (astPostRouteCTO) should be used to optimize clocks
after routing is completed. Following CTO, ECO route should be used, as
described below, to reconnect the routing.
*********????????????????????
170.Sometimes you will need to select CTS as Normal on the Route Common Options
form in order to get routing to be completed without DRC error. This will allow
tool to move clock routes further to clear errors. If that is the case, then ECO route should be run (with CTS nets selected with Minor Change Only on Route Common Options) first, and then it should be followed by Search and Repair. Prior to Search and Repair, the route options should be changed.
?????????????????????????
171.???
It uses In-Route extraction which will do incremental extraction and update of
crosstalk information as routes are changed. Therefore, there should be no need
to re-run this step. Note that In-Route extraction is approximately 5%
pessimistic to normal Astro postroute extraction; therefore, axgAdvRouteOpt
should be run before astPostRT if normal extraction is used in astPostRT, but it should be run after astPostRT if fast extraction (Real R - Virtual C) is chosen on the astPostRT form.
172.It is not recommended to correct crosstalk during Detail Routing and Search & Repair any longer since it does not run the timer and the crosstalk evaluation is not accurate. You should use axgAdvRouteOpt with only crosstalk noise, crosstalk-induced delay, and R/C reduction to fix crosstalk without buffer insertion. You should adjust the setup effort setting on the axgAdvRouteOpt form if you only want to fix crosstalk and only preserve timing during axgAdvRouteOpt.
173.Post Route Optimization (astPostRT):
Fast Extraction: This runs based on Real R and Virtual C (based on actual route) in order to do a quick optimization without a full-blown extraction. Slow extraction uses the Astro TLU capacitance models. Typically the Slow extraction is more accurate than the In-Route extraction done during axgAdvRouteOpt (which is roughly 5% pessimistic). Therefore if using Slow extraction astPostRT should be run after axgAdvRouteOpt. If using Fast extraction, then astPostRT should be run before axgAdvRouteOpt.
174.astPostRT should be used after axgAdvRouteOpt to do final tuning of the design. If desired, PARA views from Astro or StarRCXT can be used with this function. Ensure coupling information is created by either of the methods if you want to base optimizations using crosstalk-induced delays.
175.astPowerRecovery is used to do this either at the postplace optimization stage (after postplace phase 2) or after detail routing. If done after detail routing footprint matching can be done in order to minimize the extent of the design changes.
176.xtXTalkAnalysis (Xtalk analysis) (***) axgAdvRouteOpt has fixed
crosstalk violations through buffer insertion. this can make other
victims more critical, so it is better to reanalyze xtalk. Also backup cell,
to be able to step back
177.Optimizing the design flow for large designs - combining
timing, crosstalk and antenna fixing.
On Page 218,,, need to re-read...
178.HPO: High Performance Option
179.Cell > Edit-In-Place
180.Timing > Generate Parasitic View:
Notes: a) MinMax should be used for concurrent setup/hold analysis/
optimization, and b) that Store coupling mesh should be used if you wish to
analyze crosstalk using parasitic views.
181..logic, .time, .power
182.Add supplemental CLF data into nominal CLF file
antenna information (for example, gate size and diode
protection),
It is recommended
that any of these functions be added to the nominal, or typical, CLF file.
183.Note: Examples of some supplemental CLF commands: definePad,
defineGateSize, defineDiodeProtection.
184.TLU model: Table Look-Up
185.The translate linear model button is used to create simple TLU models
from linear models during the load.
186. Two mode: TLU and Linear model, linear model is less accurate///
187.STAMP and ALF format translations
188.Astro can utilize LEQ information prepared in the reference libraries or it can build that information when running on the design cell. This creates the concept of Library LEQ and Design LEQ. The advantages of this system is that it allows the library provider or CAD group to explicitly set LEQ information in reference libraries but still allows the user to override this information without modifying reference libraries.
189.Synopsys recommends that LEQ information be added as part of library preparation. This way there is no doubt of what cells are logically equivalent. For example, signal buffers, delay cells, and clock buffers may all be similar logically, but you do not want the tool interchanging them for each other.
190.designName.extension;versionNumber
191.The Synopsys applications make the following assumptions:
The layout cell if you do not include an extension.
The most recent version if you do not include a version number.
192.When you open a cell in write mode, the Synopsys application locks the cell
from write access by other users by creating a lock file
(<cellFileName>:<versionNumber>_lock). When you close the cell, the
Synopsys application removes the lock file, allowing write access to other
users.
193.When you save a cell, the Synopsys application saves the previously saved
version as a backup copy.
194.Toggle and Radio selections are options selected by form buttons for specific option categories. A toggle is used to select one or more options of an option category. A Radio is used to select only one allowable option of an option category.
195.cell library format (CLF) file,
196.A technology file defines the characteristics of a cell library, such as units of measure, graphical specifications, layer and device definitions, and design rules.
197.A CLF file provides a Synopsys application with library-specific information.
198.Top Design Format (TDF) Files:
For each top-level design in your libraries, your Synopsys directory should
contain one or more TDF files. These files provide your Synopsys application
with special instructions for planning, placing, and routing the design. For
199.
Layout cells represent the physical layout of a design.
Pin/blockage cells represent the pins and blockage areas (areas where no
routing on a particular layer can occur), the via regions (areas where vias
can be placed during routing), and the pin solutions (solutions for routing to
pins).
Netlist cells represent the logical connectivity of a design at the top level of
hierarchy.
Expanded netlist cells represent the logical connectivity of a design at
enough levels of hierarchy to provide information necessary for binding
with the physical layout.
200. notch fill & gap fill
--------------------------------------------------------------------------------
1.powerful PhySiSys" technology and the new Milkyway-DUO" (Dynamic Unified Optimization) architecture.
2. including timing, signal integrity, crosstalk, power, die size, routability and manufacturability.
3.design closure
4.synthesis netlist optimization
5.physically accurate silicon models
6.Milkyway Duo is the run-time database.
7.Astro & Apollo: most of the key algorithms have been rewritten including logic optimization, timing analysis, placement, and clock tree synthesis.
Other features have been added such as hierarchy preservation and overlap removal.
8.parasitic extraction,
9.dump out the HSPICE information
10.CG (netlist):CG: Common Graph: common graph is a bare bones netlist.
11.PDS: Placement Driven Synthesis
12.Call Back:
13.Overlap Removal:It allows functions like PDS and CTS/CTO to instantaneously determine the effects of a sized or added cell and then remove the change if it degrades performance.
14.Apollo/Saturn.
15.Some simple methods of optimization are not used by Saturn, such as gate duplication, net splitting, and inverter insertion.
16.Scan optimization includes the ability to maintain the original module ports
in the hierarchical netlist.
17.Congestion based coupling estimation for preroute extraction.
18.manufacturability issues (such as antenna checking and fixing).
19.***************************
In addition to continuing to support Synopsys .lib format, with Astro, Synopsys
adds translation of Synopsys STAMP models. In addition ALF models are also
supported. All of these are translated into Synopsys CLF format and/or Astro
TIM model format.
*****************************
Cadence: ILM model: Interface Logical Modeling
20.Create Capacitance Model: TLU Cap Models
StarRCXT ITF file,
21.ApolloToAstroCmdConversion.Map
ap2ast
22.In Apollo, timing constraints are stored in the cell database in a TDF table.
Astro will only read SDC syntax for timing constraints.
23.CEL and TIM views in Apollo,
24.Logically Equivalent Cell (LEQ) Information
25.Cell Delay Model - TLU
Wire Delay Model - AWE
26.Loading Power Supply Information
27.If loaded, crosstalk analysis will use power supply information loaded into the tool.
******************************
If not provided, crosstalk analysis will still work since it can be based on
a voltage value independent of supply value. For multiple voltage
designs, users are recommended to load the power supply information
in order to get accurate analysis since noise metrics are percentages of
the power supply. For single voltage supply designs the result will be the
same with or without the supply loaded.
*******************************
28.HCG (Hierarchical Common Graph):astInitHierPreservation
modules that must be preserved:astMarkHierAsPreserved
29. CLF
30.Read in verilog description to create .NETL view.
Expand the netlist (.NETL view) to create a .EXP view.
Create a cell view .CEL and bind netlist view .EXP.
Add Cells not in the netlist such as pwr/gnd pads.
Set power/ground ports using Preroute > Connect Ports to P/G
Initialize hierarchy preservation information using
31. expanded netlist view (.EXP),
If you want to dump a hierarchical netlist using astDumpHierVerilog, then at a
minimum, astInitHierPreservation, should be done.
32.Delete hicon ports using astRepairHierPreservation since PrimeTime can
not find these nets.
33.Backslash before hierarchical name.
Strip BackSlash
This option will strip the backslash before the hierarchy separator. In almost all cases it should be left at the default value of ON.
34.Dont use EXP view to do astInitHierPreservation, use the CEL and NETL
views.
35.Remember to set correct busStyle for the library. Users should see a
warning message on bus Style when generating hierVerilog.
36.Use astCheckHierPresConsistency. This command checks if hierarchical
information (HCG) in the cell is consistent with the flat CG. It works on a current open cell and loads CG if it is not already loaded. It generates CGHIER errors, if there is any difference in the HCG and CG data.
37.Astro can take both TCL based and non TCL based SDC constraints,
38.SDC constraints that would be generated by the write_sdc function should be avoided since they are expanded. It is better to load SDC with wildcards into Astro than an expanded SDC.
39.Often constraints used for final timing verification, or for initial synthesis, are not appropriate at all stages of physical optimization. For example, it is not correct to set propagated clocks or allow data/clock mixed paths prior to building the clock tree. Other examples include the use of case analysis.
40.Either astInitHierPreservation or cmCreateHierPorts should be run prior to loading SDC file in order that SDC constraints to hierarchical ports (which disappear during flattening) can be properly considered.
********************************
41.ExamineSDC:
set_propagated_clock
set_case_analysis
********************************
42.
TDF: Timing Setup Tabs,
43.TDF pin/pad commands will be used to control the physical location of pins and pads only. There are no timing related TDF commands in Astro.
44.SDC information is not backward compatible
45.OV, PPO
46.Timing > Write Design Constraints (astWriteDC)
Input is : SDC
47.LEQ
48.LPF:
49.TLUPlus uses Star-RCXT model generation to create TLU capacitance tables.
50.Net Delay Model
It is recommended to set Elmore prior to routing and AWE after routing.
51.There are two ways to buffer high fanout nets in Astro; during PrePlacement Optimization and using Astro CTS.
52.Typically, scan enables should be buffered by Astro CTS since the loads
will be declared as scan clock in the port types file. To keep PrePlacement
Optimization from buffering these nets simply declare the scan enable as a clock.
53.Astro will automatically handle high fanout nets during the flow; therefore, for most nets, there is no need to set a transition or cap default.
54.There is data and clock mixing causing a high fanout clock node in a critical path. This path will not be fixed by preplace optimization because the net is partially clock.
55.Setting Net Transition Defaults for Non-Clock Nets
56.Loading ataSetNetCapTransAndDelay will create a .TIM view to store the information. You should immediately save the .TIM after loading the step. The best way is to use Cell > Save All Open Cells! (geSaveAllOpenCells). In a replay script, you can avoid the query boxes that pop up for this command by doing the
following:
setDisplayMode "QueryBoxes" #f
geSaveAllOpenCells
This is especially helpful when running in nullDisplay mode.
57. COmbinational feedback loop
58.is timing path from latch to latch and both driven by same clock with
same path,
59.reports latch self loops, a situation
where a latch output may drive its input through combination logic.
60.
Currently, the design needs to be placed for astCheckDesign to work. A simple
way to do this is to use astFastPlace (geGetEditCell). Note that this
placement is not based on congestion or timing or any other normal placement
parameters. It simply places cells in legal locations.
61.The ataCompare command will provide all the information needed to back
annotate to Synopsys DC and PrimeTime.
62.The zero interconnect timing report after preplacement optimization
provides a good indicator of final timing result.
63.Zero interconnect can hide problems with SDC affecting optimization of
certain parts of a design. It is recommended that the user should evaluate
timing closely after clocks are inserted and post-place optimization is
completed and prior to proceeding to routing.
64.To run zero interconnect timing in PrimeTime, simply do not provide any
wireload models in the .lib files read by PrimeTime. The .lib files dumped by
Astro will not contain wire load models.
65.ataCompare:
This will also allow current Astro timing constraints and Synopsys
CLF information to be translated to Synopsys format so that
PrimeTime or DC can use the same constraints and timing
information Astro uses.
ataCompare is meant to aid debugging in the case that the user does not have
access to the original .lib files. It is not recommended for production flow
because only limited QA is done. Synopsys recommends always using original
.lib files when comparing Astro to PrimeTime.
66.It is design dependent. However, in general we would like to see pre-route RC results in reasonable but little pessimistic range than post-route in order to predict design closure quality and achieve consistent design convergence.
67.To make preroute a little more pessimistic use the settings below
68.Adjusting Preroute Pessimism/Optimism of Caps
69.Guideline would be to make preroute 3-5% pessimistic at most, and then use
route optimizations to close remaining nets. Settings to adjust preroute
capacitance/resistance in Astro:
axSetRealParam "ek" "capMultiplier" 1.05
axSetRealParam "ek" "resMultiplier" 1.05
70.Checking TLU Cap Model Parameters
71.Geometry Scaling Factor:
72.Max Distance to Extract Lateral Capacitance:
Also in technology file there are Cap Multiplier (Individual) settings for
each layer. Apollo and Astro both do take them
73.TLUPlus models are generated using grdgenxo; to create them you need a
description of the process technology in Interconnect Technology Format (ITF),
which may be supplied by the foundry or created by the user. A map file will also be needed, to map the process layers to the Milkyway library technology file.
74,Interconnect Technology Format (ITF)
75.Soft blockages prevent cell instances from being placed inside except for cell instances that are either fixed or softfixed.
76.(hard or soft) placement blockage.
77.A soft-fixed cell instance cannot legally stay within hard placement blockages.
78.the placer engine sees soft as hard, but optimization commands see soft as non-existent.
79.Assign a level shifter cell from one voltage group to another using
astSetLevelShifter.
80.Connections between scan outputs and scan inputs in a scan chain may not be
optimal for routing after placement. However, now, scan clocks often run at
higher frequencies so that the tool needs to optimize them as well. In addition
hold times need to be fixed after scan flipflops are placed and the chain
connections are optimized.
81.The preferred method to reconnect and optimize is to do it after placement and clocks are inserted and prior to post placement optimization.
This would allow
postplacement optimization to optimize the chain for timing as needed.
If you do not want postplacement optimization to work on the re-connected
chain, then wait until after postplacement optimization to reconnect the chain.
82.dbMarkScanPortPairs and dbDumpScanPortPairs should be used if a
cell has multiple scan input and output ports.
83.This function performs a quick placement, high-fanout collapse, high-fanout net synthesis, gate-sizing, moving-cell, buffer/inverter bypassing, buffer insertion, inverter insertion, gate-duplication, net-splitting, area-recovery, and remapping.
The netlist changes will apply cell movement so ECO-place will be invoked. Overlap Removal (OV) is not invoked during prePlace optimization.
84.Therefore, it is recommended to rebuffer these in Astro based on the actual
physical placement. Setting the value lower tends not to improve optimizations much, but can increase the runtime since Astro must rebuffer these nets. Setting the value to 1 will remove all buffers from the design.
85.In benchmarks it has been found that when synthesis inserts buffers for fanouts greater than 10 it can interfere with Astro optimizations and increase congestion.
86.Area Recovery will eliminate buffers and downsize cells. By default the
utilization at which this occurs is 50% - as specified on the timing setup panel. Use the timing setup panel to lower this threshold if you want more recovery to occur.
87.Ideal Optimization will try to optimize the design with zero interconnect. On large designs it may be better to turn this off in order to save run-time.
88.Enforce Full Place makes the tool do a full quick placement before trying to fix high fanout nets. If not selected it will just run ECO placement.
*************************************
89.Astro, our strategy has been, at an earlier stage, we need to do more massive changes such a HFN opt before the detailed placement begins.
*************************************
90.Release Note: Max Transition and Max Capacitance are no longer optimized by
preplacement optimization nor placement with ipo. It is intended that the first
time transition and capacitance constraints are fixed is during postplacement
phase 1 optimization.
91.If the number is very negative, the user should look at the critical path with zero interconnect timing. The only acceptable source for a large negative number is if data and clock mix.
If data/clock mixing is the cause of the
high slack, turn off mixed edges during timing analysis and redo zero
interconnect timing after preplace optimization.
92.quick Boolean matching
structural-based matching
93.max transition and max capacitance are concurrently optimized
during postplacement and postrouting optimizations.
94.pdsHFNOptimization can be used to buffer non clock nets. This is actually the function built into the HFN fixing contained in preplace optimization. It can be run stand alone after a placement exists. Some users may find it more convenient to buffer large high fanout nets, like resets or enables, using this function after real placement is finished instead of during preplacement optimization. ataSetNetCapTransAndDelayTime should be set on the net to specify a realistic capacitance, delay, and transition for the net and to prevent HF optimization during preplacement optimization.
95.How can I find all High Fanout Nets in a design? Use astDumpHFN:
Syntax: astDumpHFN n
This will dump out nets with n or more pins on it.
96.Useful skew is a method of intentionally skewing a clock in order to improve the timing on a circuit.
97.There are two basic flows given in the Astro Primer: CTS with Useful Skew, and Useful Skew Budgeting.
Useful Skew Budgeting normally be done at this stage of the flow - after preplacement and prior to placement.
98.The first uses
optimizes the design completely using the useful skew budget and then
recalculates useful skew prior to running CTS, and the second runs CTS based
on the original budget and then finishes the optimization. It is recommended to
use the first flow in most cases - since it will account for errors in the original budgeting.
99.postplace optimization phase 1
postplace optimization phase 2
100.The Constraint File on this form refers to a file that contains user-defined cell clusters that the placer should attempt to place together. This allows the user to specify master and instance padding, net weights, and cell clusters.
101.Timing-driven (including IPO)
Astro Place provides a smooth trade-off from 1 to 10 with 1 having more routability, and 10 having more emphasis on timing.
102.Incremental Place
This is the same function as found in Astros ECO Placer.
103.Macro and I/O Net Weighting
Macro nets are defined as nets connected to any macro pins.
104.Search and Refine capability.
105.User Place uses Overlap Removal (OV) package to incrementally remove
overlap.
106.Dump Time Borrow Script: This is primarily for back annotation purposes
(mainly to Synopsys PrimeTime). The script can be used to feed-back the
amount of borrowing Astro is using for latch based designs. Synopsys has found that you must use aggressive borrowing in order to optimize latch based designs. The borrowing script provides a way to minimize any correlation discrepancy.
107.astEdit can be used on designs after placement, after global route, or
after routing.
108.astChangeNetlist:
Force Change: This will allow you to change the netlist no matter what. For example, if the net is dont touch, clock net, etc. Therefore, the user must suffer the consequences if they try something wrong.
109. astEdit & astChangeNetlist
110.Since this is done in the middle of
placement, the timing result will not take into account all of the placement
moves associated with optimization -- this is the reason POST can be worse
than IN (if there were placement moves due to sizing, buffers, etc. that have
not been accounted for in the IN place number).
111.Timing/Library Debug Manager
The purpose is to provide some automation to verifying the timing analysis results vs. actual circuit simulation. In addition, the timing models can be reverified against the sub circuit information.
112.slew derate factor, etc.
113.The data book will quote three values of VDD, e.g.,
1.62, 1.80, 1.98
worst-case VDD = min
best-case VDD = max
typical-case VDD
The GUI form has a box where the user can type the value of VDD. Suppose that
the user has picked the condition to be the worst case. The user should type the worst-case VDD---
114.SPELLING OF VDD, VSS
Suppose that the vendor has spelled VDD as $VDD.
sed s/\$VDD/VDD/g subckt.sp > temp.sp
mv temp.sp subckt.sp
Suppose that the vendor has spelled VSS as $VSS.
sed s/\$VSS/VSS/g subckt.sp > temp.sp
mv temp.sp subckt.sp
115.DETERMINING THE PROCESS TAG
.LIB MODELS SlowSlow
The third phrase is the process tag---SlowSlow in the example above.
116.Stage Delay Checker:
A stage comprises a (signal) net, the driver of the net and the load(s) of the net. A stage is uniquely identified by the net name.
117.Note that the directory demTemp is temporary. If the user closes the Debugger Manager window, the directory will be removed automatically.
118.Topology Based Optimizations
Topology-based optimization is used throughout the Astro design closure flow.
119.placement and routing blockages.
120.Topology based fixing can be run at the placement stage, based on a quick global route, in order to correctly predict this situation and place the buffer in the optimum location.
121.Post-Placement Optimization Phase 1:]
This is the step where we take advantage of topology based optimizations, as
discussed above, prior to global routing or real routing.
Typically, it should only be run once. Depending on if postplace phase 2 is run before or after CTS, phase 1 will be either run before CTS or before initial phase 2 optimization (if phase 2 is done prior to CTS). In addition, it is recommended to redo high fanout net fixing that may have been done previously.
122.(phase 1)
Redo HFN Synthesis
At this stage we can base the high fanout clustering on the final placement. This tends to relieve congestion in the design. Previously, the purpose of high fanout optimization was to aid optimizations and during preplacement the clustering is based on a fast placement which is enough for that purpose. This step will do high fanout net collapse and then redo high fanout net fixing.
123. Fix Max Length
On some designs it helps to place buffers/inverters at specified lengths prior to doing detailed optimization. Typically these are large designs or designs with a lot of macro blockages.
124. Phase I:
setup time is not considered. Postplace phase 2 (astPostPS) should be used to
close the timing by doing detailed optimizations. The reason the two are not on
one form is allow the user more control. Postplace phase 1 (astPostPS1) is
typically done once to get the buffers inserted based on the topology. Phase 2
can be done as many times as desired, for example, prior to and after
propagating clocks.
125.******************************
PostPS I can only be done oce,
PostPS II can be done many times..
**********************************
126.Clocks must be inserted after placement. The overlap removal engine minimizes cell disturbances during CTS and CTO; therefore, when inserting clocks after placement, the timing result does not change much. Likewise because of overlap removal, postplace opt does not disturb the CTS result significantly. Also CTO can be run after postplace opt.
127.****
In patch 2 of Astro In-place CTS (concurrent CTS) has been removed
because of difficulties of getting the function to work dependably and
non-proven results. Users should build clocks after placement and
before postplace optimizations and then run clock tree optimizations
after postplace optimizations.
*************************************************************
128.Flow: PostPS I -> CTS -> PostPS II -> CTO ( For Patch 2)
*************************************************************
129.Clock Tree Synthesis (CTS) using global skew is the traditional method of
inserting clocks where CTS tries to make all the clock arrival times the same.
Typically designers looked for global skews that were 200-300 ps. With higher
clock frequencies the requirement for lower skew is needed since the clock
period is less. For example, 200ps skew for a 500MHz clock (2ns period)
represents 10% of the clock cycle. Often it is difficult to reduce the global skew further on a design; however, if local skew is used, then the tool only tries to reduce the skew on logically related flip-flops while ignoring the skew between non related flip-flops. This technique can reduce the skew on related flip-flops lower than the global skew of the design. In addition, if the global skew is too small, then there can be power problems due to the simultaneous switching of all flip-flops in the design at nearly the same time.
130. Global CTS & Local CTS....
131.**********Flow
The basic idea in this flow is to:
PreplaceOpt --> gives better netlist to placer
Placement with In-Place Optimization --> minimize congestion and timing
PostPlace Opt Phase 1 --> redo HFN fixing and use topology based design
rule fixing for transition, cap, length, and crosstalk
Build the clocks using global skew
Local Skew can increase the runtime of initial CTS
Optimize the design using PostPlace Opt Phase 2
Can propagate the clocks at this time if desired
Optimize the clock tree using Global or Local Skew
Re-optimize using PostPlace Opt Phase 2 with clock propagation (if
desired)
**************************
132.Post-Placement Clock Flow - Useful Skew Flow:
Propagate Clocks via SDC file
133.At this time it is not recommended to use Clock Tree Optimizations
with useful skew. In the future this may be a valid addition to the
above flow.
134.Currently the best way to control the amount of useful skew is to adjust the clock period.
135.Astro CTS can be used on gated and non gated trees by selecting the Gated Clock Tree button near the top of form.
136.To ensure certain buffers are not used during embedded CTO, please set
astDontUse property on the buffer - CTO will take any LEQ buffer set
by astSetClockCell (or in library is astSetClockCell is not specified).
Often, strong buffers create electromigration problems.
137.The clocks are considered in the order given on the astClockOptions form. It is recommended to put the most critical clock last in order to get best synthesis results.
138.In order to handle gated clock tree, we developed GCTS.
139.Starting in patch 3, CTA (clock tree analyzer) is able to search the optimal parameters for CTS. If you want to set parameters yourself (like previous releases), please turn OFF CTA, using:
axSetIntParam "acts" "CTA" 0
140.Basically astCTS will convert transition, fanout, and
cap to a capacitance value and then selects the smallest one.
141.Sometimes you may want to fix buffers/inverts after CTS to prevent them from moving in the future. Also, sometimes you want to CTS not to move sinks during/after CTS. Normally both of these are not necessary.
142.CTS produces a file of nets (net.acts) it creates. Prior to patch 1,
customers utilized this file to determine which nets are part of the clock
network. However, this file may be incomplete. If you run astCTS more
than once, you should rename the file before subsequent runs. Also, CTO
can delete/add nets, so that the nets contained in net.acts is no longer
valid. ataDumpClockNets is the safest way to ensure you have dumped
all clock nets.
143.Block vs. Top on the astCTS form
Block should be used on designs consisting of mostly standard cells. On the
following design types,top should be used:
chip level designs
big designs (e.g. size > 1mm^2)
macros are placed inside the design.
Qespecially if standard cells are placed around the macros
When top is selected, some clusters are identified based on their locations. Each cluster is driven by a sub-tree. The main purpose of this option is try to put fanout pins to a same branch if they are in the closed area.
******************************************
144.Clocks with Logic Overlay:
As a conclusion, we recommend to customers to synthesize two clocks at the
same time if they have logic overlap.
******************************************
145.dummy load insertion,
146.Embedded CTO
Embedded CTO is the built-in CTO capability inside CTS. It includes buffer
resizing, dummy load insertion, level adjustment, etc. The difference of
embedded CTO to post-route (or standalone) CTO is that the CTS engine is able
to dynamically refine its clock tree structure within the process of generating
clock tree, while post-route CTO focuses on further skew refinement after most
of the layout implementation (especially clock tree routing) is complete.
147.During CTS the buffers are controlled by the selection on the clock options form. During CTO the tool will use all LEQ buffers defined in the library or from astSetClockCell (if set). To keep from using some buffers, the user can use astSetDontUse. Note that astSetClockCell prevents other Astro Optimizations
from using the specified buffers/inverters for normal optimizations, so users
must be careful in this area.
148.To control which delay cells astSetDelayCell can be used. The specified delay cells will not be used by normal Astro optimizations except hold time fixing. Alternatively, the user can use separate functions specifically for Buffer Sizing and Dummy Load Insertion which provide greater control on the form for buffers, delay cells, and nets used.
149.AstroCTS:]
Sync Pins & Ignore Pins (??????????))
150.Buffering Non Clock Nets using CTS:
(1) Define a clock using tcl - create_clock;
(2) To set all inputs of a net to be synchronous,axSetIntParam
set_default_trigger_edge
(3) set all back;
*******************************************
151.Buffering Non Clock Nets using CTS: (Three Method.)
(1) Instead of setting the trigger edge parameter,(above)
(2) dbDefineSyncPin statements can be created for each sink on the desired net
(3) pdsHFNOptimization can also be used as described at the end of the
preplacement optimization chapter.
*******************************************
152.Basic CTS is the Astro equivalent of Apollos MCTS (multi-level CTS). It allows the user to provide a configuration file that completely specifies a non-gated clock tree structure and Astro will build it optimally.
153.Synopsys recommends customers build specific dummy load cells instead of
using generic buffers. Dummy load cells should only have input pin capacitance
and no logic function so that they have the smallest possible cell size to minimize the effect of additions on the layout utilization and congestion.
154.Incremental CTS:
A design may have some ECO changes (such as deletion of FFs, addition of FFs
and relocation of FFs). If these ECO changes are made after routing, we
recommend you use ECO CTS instead of CTO. Since CTO may break a lot of
routed wires, change a lot of cells locations and even change the netlist. The ECO CTS will consider routing costs while synthesizing and optimizing the clock tree.
155.One method is to optimize the design at postplacement is to run postplacement opt several times:
156.astPowerRecovery is used to do this either at the postplace optimization stage (after postplace phase 2) or after detail routing. If done after detail routing footprint matching can be done in order to minimize the extent of the design changes.
157.Effects of SDC on Timing Analysis and Optimization:
One technique to help check if there is a problem with max transition and max
capacitance constraints is to examine various timing reports:
(1) generate timing report with normal settings - ensure default clock is enabled on the timing setup form
(2) remove all case analysis statements and generate timing report;
(3) remove disable timing statements from the SDC and generate timing report
If the number of max transition or max capacitance constraints changes, the
design should be optimized to fix the problems. If setup and hold constraints
change, then at a minimum optimize only transition and capacitance. If setup and hold are the same as the normal operating conditions, then it does not hurt to optimize setup and hold, as well as transition and capacitance, at the same time.
158.Astro is designed to accurately predict the routing capacitance. Users should find that the Astro result is slightly pessimistic and will improve after routing. It is not expected that any significant increase in slack will occur between placed timing results and routed timing results.
159.Similar to Apollo, it is recommended that critical clocks in Astro be routed before other signals so that they will have the most direct routing. The easiest way to do this is to use Route > Route Net Group and select All Clock Nets on the form.
160.By default Astro will typically route more on the upper layers. If you want to influence this, i.e. push routes more toward top or more toward the bottom,
adjust routing cost...
161.The best routability will be achieved by using the defaults. Adjusting the
costs to use more upper layers (in order to utilize layers with more
desirable properties), for example, may make some designs unroutable.
It is recommended to only adjust the parameters after you have gotten a
trial pass to route, or almost route, clean.
162.The parameter (axSetIntParam "route" "layerExtraCostByRC" 2) used to be recommended, but it was found that this only works on designs that use a process with very high-resistance vias and with some customers with very different pitch/width/RC for different layers. In many cases it would make designs unroutable; therefore, it is no longer recommended.
163.To see all available parameters use: axPrintParams all . To see only the route ones use axPrintParams route . Note that there are global route, trackassign,
164. Route:
during global route, track assign, and detail route.
165.in-route BI/GS
166.The recommend flow to fix crosstalk is to set prevention during global route and track assign. Then achieve zero DRC violations after Search and Repair. Run axgAdvRouteOpt (discussed later) without crosstalk to optimize timing - if significant timing improvement is necessary. Then run crosstalk analysis (xtXTalkAnalysis) followed by axgAdvRouteOpt with crosstalk to optimize timing and crosstalk.
167.Release Note: It is not recommended to correct crosstalk during Detail Routing and Search & Repair any longer since it does not run the timer and the crosstalk evaluation is not accurate. See Chapter13 for more details.
168.Global Route Optimization (astPostGR):
This function may not always improve timing and should not be the standard
flow, but can help on some designs.
169.Post Route CTO (astPostRouteCTO) should be used to optimize clocks
after routing is completed. Following CTO, ECO route should be used, as
described below, to reconnect the routing.
*********????????????????????
170.Sometimes you will need to select CTS as Normal on the Route Common Options
form in order to get routing to be completed without DRC error. This will allow
tool to move clock routes further to clear errors. If that is the case, then ECO route should be run (with CTS nets selected with Minor Change Only on Route Common Options) first, and then it should be followed by Search and Repair. Prior to Search and Repair, the route options should be changed.
?????????????????????????
171.???
It uses In-Route extraction which will do incremental extraction and update of
crosstalk information as routes are changed. Therefore, there should be no need
to re-run this step. Note that In-Route extraction is approximately 5%
pessimistic to normal Astro postroute extraction; therefore, axgAdvRouteOpt
should be run before astPostRT if normal extraction is used in astPostRT, but it should be run after astPostRT if fast extraction (Real R - Virtual C) is chosen on the astPostRT form.
172.It is not recommended to correct crosstalk during Detail Routing and Search & Repair any longer since it does not run the timer and the crosstalk evaluation is not accurate. You should use axgAdvRouteOpt with only crosstalk noise, crosstalk-induced delay, and R/C reduction to fix crosstalk without buffer insertion. You should adjust the setup effort setting on the axgAdvRouteOpt form if you only want to fix crosstalk and only preserve timing during axgAdvRouteOpt.
173.Post Route Optimization (astPostRT):
Fast Extraction: This runs based on Real R and Virtual C (based on actual route) in order to do a quick optimization without a full-blown extraction. Slow extraction uses the Astro TLU capacitance models. Typically the Slow extraction is more accurate than the In-Route extraction done during axgAdvRouteOpt (which is roughly 5% pessimistic). Therefore if using Slow extraction astPostRT should be run after axgAdvRouteOpt. If using Fast extraction, then astPostRT should be run before axgAdvRouteOpt.
174.astPostRT should be used after axgAdvRouteOpt to do final tuning of the design. If desired, PARA views from Astro or StarRCXT can be used with this function. Ensure coupling information is created by either of the methods if you want to base optimizations using crosstalk-induced delays.
175.astPowerRecovery is used to do this either at the postplace optimization stage (after postplace phase 2) or after detail routing. If done after detail routing footprint matching can be done in order to minimize the extent of the design changes.
176.xtXTalkAnalysis (Xtalk analysis) (***) axgAdvRouteOpt has fixed
crosstalk violations through buffer insertion. this can make other
victims more critical, so it is better to reanalyze xtalk. Also backup cell,
to be able to step back
177.Optimizing the design flow for large designs - combining
timing, crosstalk and antenna fixing.
On Page 218,,, need to re-read...
178.HPO: High Performance Option
179.Cell > Edit-In-Place
180.Timing > Generate Parasitic View:
Notes: a) MinMax should be used for concurrent setup/hold analysis/
optimization, and b) that Store coupling mesh should be used if you wish to
analyze crosstalk using parasitic views.
181..logic, .time, .power
182.Add supplemental CLF data into nominal CLF file
antenna information (for example, gate size and diode
protection),
It is recommended
that any of these functions be added to the nominal, or typical, CLF file.
183.Note: Examples of some supplemental CLF commands: definePad,
defineGateSize, defineDiodeProtection.
184.TLU model: Table Look-Up
185.The translate linear model button is used to create simple TLU models
from linear models during the load.
186. Two mode: TLU and Linear model, linear model is less accurate///
187.STAMP and ALF format translations
188.Astro can utilize LEQ information prepared in the reference libraries or it can build that information when running on the design cell. This creates the concept of Library LEQ and Design LEQ. The advantages of this system is that it allows the library provider or CAD group to explicitly set LEQ information in reference libraries but still allows the user to override this information without modifying reference libraries.
189.Synopsys recommends that LEQ information be added as part of library preparation. This way there is no doubt of what cells are logically equivalent. For example, signal buffers, delay cells, and clock buffers may all be similar logically, but you do not want the tool interchanging them for each other.
190.designName.extension;versionNumber
191.The Synopsys applications make the following assumptions:
The layout cell if you do not include an extension.
The most recent version if you do not include a version number.
192.When you open a cell in write mode, the Synopsys application locks the cell
from write access by other users by creating a lock file
(<cellFileName>:<versionNumber>_lock). When you close the cell, the
Synopsys application removes the lock file, allowing write access to other
users.
193.When you save a cell, the Synopsys application saves the previously saved
version as a backup copy.
194.Toggle and Radio selections are options selected by form buttons for specific option categories. A toggle is used to select one or more options of an option category. A Radio is used to select only one allowable option of an option category.
195.cell library format (CLF) file,
196.A technology file defines the characteristics of a cell library, such as units of measure, graphical specifications, layer and device definitions, and design rules.
197.A CLF file provides a Synopsys application with library-specific information.
198.Top Design Format (TDF) Files:
For each top-level design in your libraries, your Synopsys directory should
contain one or more TDF files. These files provide your Synopsys application
with special instructions for planning, placing, and routing the design. For
199.
Layout cells represent the physical layout of a design.
Pin/blockage cells represent the pins and blockage areas (areas where no
routing on a particular layer can occur), the via regions (areas where vias
can be placed during routing), and the pin solutions (solutions for routing to
pins).
Netlist cells represent the logical connectivity of a design at the top level of
hierarchy.
Expanded netlist cells represent the logical connectivity of a design at
enough levels of hierarchy to provide information necessary for binding
with the physical layout.
200. notch fill & gap fill
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