原创【数字IC】高级数字 IC 设计（10）Sobel 设计

 2023-3-18 21:54  525 5 5 分类: FPGA/CPLD 文集: 数字IC

Sobel算法是做图像的必备技能，其设计流程如下：

mif文件的制作→ 调用ip核生成rom以及仿真注意问题→ 灰度处理→ 均值滤波：重点是3*3 像素阵列的生成→ sobel边缘检测→ 图片的显示→ 结果展示。

在技术上，Sobel算法是一离散性差分算子，用来运算图像亮度函数的灰度之近似值。在图像的任何一点使用此算子，将会产生对应的灰度矢量或是其法矢量。

module Sobel(</p>
clk_i,
rst_n,
iStart,
iData,
oData,
data121,
oStart
);
input clk_i;
input rst_n;
input [7:0] iData;
input iStart;
output [7:0] oData;
output oStart;
output [9:0] data121;
//=======================================================
//reg & wire
//=======================================================
reg [7:0] oData;
wire oStart;
//for Row buffer
wire [7:0] Data_Row0,Data_Row1,Data_Row2;
//for data121
wire [9:0] data121;
reg [9:0] DataV0,DataV1,DataV2;
assign Data_Row0 = iData;
//for odata
wire [9:0] DataSub,Subina,Subinb;
//for ostart delay
reg [2:0] Start_delay;
//=======================================================
//row buffer
//=======================================================
Row_Buffer Row_Buffer (
.clock(clk_i),
.shiftin(iData),
.taps9x(Data_Row2),
.taps4x(Data_Row1)
);
//=======================================================
//data121
//=======================================================
assign data121 = {2'd0,Data_Row0} + {1'b0,Data_Row1,1'b0}
+ {2'd0,Data_Row2};
always @ (posedge clk_i or negedge rst_n)begin
if(!rst_n)begin
DataV0 <= 10'd0;
DataV1 <= 10'd0;
DataV2 <= 10'd0;
end
else begin
DataV0 <= data121;
DataV1 <= DataV0 ;
DataV2 <= DataV1 ;
end
end
//=======================================================
//oData
//=======================================================
assign Subina = (DataV0 > DataV2) ? DataV0 : DataV2;
assign Subinb = (DataV0 > DataV2) ? DataV2 : DataV0;
assign DataSub = Subina - Subinb;
always @ (posedge clk_i or negedge rst_n)begin
if(!rst_n)begin
oData <= 8'd0;
end
else begin
if(DataSub[9:8] == 2'd0)
oData <= DataSub[7:0];
else
oData <= 8'hff;
end
end
//=======================================================
//oStart whole delay will be 3
//=======================================================
always @ (posedge clk_i or negedge rst_n)begin
if(!rst_n)begin
Start_delay <= 3'd0 ;
end
else begin
Start_delay[0] <= iStart;
Start_delay[1] <= Start_delay[0];
Start_delay[2] <= Start_delay[1];
end
end
assign oStart = Start_delay[2];
reg [9:0]Hcount;
reg [8:0]Vcount;
always @ (posedge clk_i or negedge rst_n)begin
if(!rst_n)begin
Hcount <= 10'd0;
Vcount <= 9'd0;
end
else begin
if(oStart)begin
if(Hcount == 10'd639 && Vcount == 9'd479)begin
Hcount <= 10'd0;
Vcount <= 9'd0;
end
else if(Hcount == 10'd639)begin
Hcount <= 10'd0;
Vcount <= Vcount + 1'b1;
end
else begin
Hcount <= Hcount + 1'b1;
end
end
else begin
Hcount <= 10'd0;
Vcount <= 9'd0;
end
end
end
endmodule

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