原创 FPGA读写2PORTRAM过程分析3

READ:

           begin

              ioRDY0_SLRDn<='b1;//读结束要拉高

              sram_rden<='b0;

              sram_wren<='b0;

              //SRAM读写都没有使能

              if(sram_a_i!=ADDR_FULL)

                     STATE<=DATA_READY;

//如果SRAM的地址到了结尾处，说明写SRAM结束了，将状态转化为读取USBFIFO结束状态。这时候，可以读取SRAM了。注意这里又是读，又是写的。看清楚对象，就明白了。这上面的状态，就是大写的那个已经CASE的变量，是从FPGA对USBFIFO来说的。

                  else

                     STATE<=READ_END;

            End

READ_END:

               begin

                     ioRDY0_SLRDn<='b1;

                     oPA2_SLOEn<='b1;

                     oPA4_FIFO0<='b0;

                     oPA5_FIFO1<='b0;

                     sram_a_i<='h1fff; //2portRAM输入地址，也就是写地址为1FFF，就是结尾处。

                     STATE<=WRITE_EVENT;

                End

再说一遍，大写的状态，CASE的变量，是从FPGA对USBFIFO来说的，所以接下来是读取SRAM的内容，把这个内容写到USBFIFO上去，状态为WRITE_EVENT。同样的原理不多说了。

WRITE_EVENT:  //read sram to USB ep6

                  begin

                      oPA4_FIFO0<='b0;

                      oPA5_FIFO1<='b1;

                      oe<='b1;

                      wr_flag<='b0;

                      STATE<=POINT_TO_IN_FIFO;

                  end

POINT_TO_IN_FIFO:

                   begin

                       sram_a_o<=sram_a_o+1;  //SRAM_A_O=0000了

                       datacnt<=datacnt+1;   //这个时候DATACNT=0000了

                       sram_rden<='b1;

                       sram_wren<='b0;

                       //STATE<=WRITE_READY;

                       STATE<=WRITE_ADD;

                   End

WRITE_ADD:  

                   Begin

                         ram_rden<='b1;

                         sram_wren<='b0;   

                         sram_a_o<=sram_a_o+1;       //这个时候SRAM_A_O=0001了

                         datacnt<=datacnt+1;                //这个时候DATACNT=0001了

                         STATE<=WRITE_READY;

                   End

这个状态，就是多加了一次地址的值，有什么用，以后继续研究，现在放过。

WRITE_READY:

                   begin

                   if(ioCTL1_FLAGB) //not full

                          begin

                            if (datacnt==sram_a_o)

                                 begin

                                 data_wr<=sram_d_o;

                                 end

                             else

                                   begin

                                   fifodata[datacnt-sram_a_o]<=sram_d_o;

                                   fifodata[datacnt-sram_a_o-1]<=fifodata[datacnt-sram_a_o];

                                   data_wr<=fifodata[datacnt-sram_a_o-1];

                                   datacnt<=datacnt-1;

                                  end

                            ioRDY1_SLWRn<='b0;

                            ioRDY0_SLRDn<='b1;

                            STATE<=WRITE;

                            end

                   else

                            begin

                            //data_wr1<=sram_d_o;

                            ioRDY1_SLWRn<='b1;  ///??

                            ioRDY0_SLRDn<='b1;  ///?

                            //STATE<=WRITE_READY;  ///?

                            if (FFlagA==0)

                                     begin

                                         datacnt<=datacnt+1;

                                               fifodata[datacnt-sram_a_o]<=sram_d_o;

                                               FFlagA<=FFlagA+1;

                                     end

                                     else fifodata[datacnt-sram_a_o]<=sram_d_o;

                            STATE<=WRITE_READY;

                            end

                   end

关于那个FLAGA,FLAGB,FLAGC,代表PL，EMPTY,FULL标志。